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101 innovation drive san jose, ca 95134 (408) 544-7000 http://www.altera.com cyclone ii device handbook, volume 1 cii5v1-3.1
copyright ? 2007 altera corporation. all righ ts reserved. altera, the programmable solu tions company, the stylized altera logo, specific device des- ignations, and all other words and logos that are identified as tr ademarks and/or service marks ar e, unless noted otherwise, th e trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of the ir respective holders. al- tera products are protected under numerous u.s. and foreign patents and pending app lications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice . altera assumes no responsibility or liability arising out of t he ap- plication or use of any info rmation, product, or service desc ribed herein except as expressly agreed to in writing by altera corporation. altera customers are advised to obtain the latest ve rsion of device specifications before relying on any published in- formation and before placing orders for products or services . ii altera corporation
altera corporation iii contents chapter revision dates ........................................................................... xi about this handb ook ............................................................................ xiii how to contact altera .......................................................................................................... ................ xiii typographic conventions ........................................................................................................ ............ xiii section i. cyclone ii devi ce family data sheet revision history ............................................................................................................... ..................... 1?1 chapter 1. introduction introduction ................................................................................................................... ......................... 1?1 low-cost embedded processing solutions .................... .............................................................. 1?1 low-cost dsp solutions ......................................................................................................... ........ 1?1 features ....................................................................................................................... ............................ 1?2 document revision history ...................................................................................................... ........... 1?8 chapter 2. cyclone ii architecture functional description ......................................................................................................... ................. 2?1 logic elements ................................................................................................................. ...................... 2?2 le operating modes ............................................................................................................. ........... 2?4 logic array blocks ............................................................................................................. ................... 2?7 lab interconnects .............................................................................................................. .............. 2?8 lab control signals ............................................................................................................ ............. 2?8 multitrack interconnect ........................................................................................................ ............. 2?10 row interconnects .............................................................................................................. ............ 2?10 column interconnects ........................................................................................................... ......... 2?12 device routing ................................................................................................................. .............. 2?15 global clock network & phase-locked lo ops ............. ........... ........... ........... ......... ......... ......... ...... 2?16 dedicated clock pins ........................................................................................................... .......... 2?20 dual-purpose clock pins ........................................................................................................ ...... 2?20 global clock network ........................................................................................................... ........ 2?21 global clock network distribution ............................................................................................ 2? 23 plls ........................................................................................................................... ....................... 2?25 embedded memory ................................................................................................................ ............. 2?27 memory modes ................................................................................................................... ............ 2?30 clock modes .................................................................................................................... ................ 2?31 m4k routing interface .......................................................................................................... ........ 2?31 embedded multipliers ........................................................................................................... ............. 2?32
iv altera corporation cyclone ii device handbook, volume 1 contents multiplier modes ............................................................................................................... ............. 2?35 embedded multiplier routing interface ..................................................................................... 2?36 i/o structure & features ....................................................................................................... ............. 2?37 external memory interfacing .................................. .................................................................. ... 2?44 programmable drive strength .................................................................................................... .2?49 open-drain output .............................................................................................................. .......... 2?50 slew rate control ............................................. ................................................................. ............. 2?51 bus hold ....................................................................................................................... ................... 2?51 programmable pull-up resistor .................................................................................................. 2?51 advanced i/o standard support ................................................................................................ 2? 52 high-speed differential interfaces ............................................................................................. .2?53 series on-chip termination ..................................................................................................... .... 2?55 i/o banks ...................................................................................................................... .................. 2?57 multivolt i/o interface ........................................................................................................ ......... 2?60 chapter 3. configuration & testing ieee std. 1149.1 (jtag) boundary scan support ........... ........... ........... ........... ......... ......... ......... ...... 3?1 configuration .................................................................................................................. ....................... 3?5 operating modes ................................................................................................................ ................... 3?5 configuration schemes .......................................................................................................... ............... 3?6 cyclone ii automated single ev ent upset detection ...................................................................... 3?7 custom-built circuitry ......................................................................................................... ........... 3?7 software interface ............................................................................................................. ................ 3?7 document revision history ...................................................................................................... ........... 3?8 chapter 4. hot socke ting & power-on reset introduction ................................................................................................................... ......................... 4?1 cyclone ii hot-socketing specifications ......................................................................................... ... 4?1 devices can be driven before power-up ..................................................................................... 4?2 i/o pins remain tri-stated during power-up ............................................................................ 4?2 hot-socketing feature implem entation in cyclone ii devices ....................................................... 4?3 power-on reset circuitry ....................................... ................................................................ ............. 4?5 "wake-up" time for cyclone ii devices ....................................................................................... 4?5 conclusion ..................................................................................................................... ......................... 4?7 document revision history ...................................................................................................... ........... 4?7 chapter 5. dc characteristics & timing specifications operating conditions ........................................................................................................... ................ 5?1 single-ended i/o standards ..................................................................................................... ..... 5?5 differential i/o standards ..................................................................................................... ......... 5?7 dc characteristics for different pin types ..................................................................................... 5?11 on-chip termination specifications ............................. .............................................................. 5? 12 power consumption .............................................................................................................. ............. 5?13 timing specifications .......................................................................................................... ................ 5?14 preliminary & final timing specifications ................................................................................. 5?14 performance .................................................................................................................... ................ 5? 15 internal timing ................................................................................................................ ............... 5?18
altera corporation v cyclone ii device handbook, volume 1 contents cyclone ii clock timing parameters ........................................................................................... 5?2 2 clock network skew adders ...................................................................................................... .5?28 ioe programmable delay ......................................................................................................... .... 5?29 default capacitive loading of different i/o standards . ......................................................... 5?30 i/o delays ..................................................................................................................... .................. 5?31 maximum input & output clock rate ....................................................................................... 5?43 high speed i/o timing specifications ....................................................................................... 5?52 external memory interf ace specifications .................................................................................. 5?60 jtag timing specifications ..................................................................................................... ..... 5?61 pll timing specifications ...................................................................................................... ...... 5?63 duty cycle distortion .......................................................................................................... ......... ...... 5?64 dcd measurement techniques ................................................................................................... 5? 65 document revision history ...................................................................................................... ......... 5?71 chapter 6. reference & ordering information software ....................................................................................................................... ........................... 6?1 device pin-outs ................................................................................................................ ..................... 6?1 ordering information ........................................................................................................... ................ 6?1 document revision history ...................................................................................................... ........... 6?2 section ii. clock management revision history ............................................................................................................... ..................... 6?1 chapter 7. plls in cyclone ii devices introduction ................................................................................................................... ......................... 7?1 cyclone ii pll hardware overview ................................................................................................ .. 7?2 pll reference clock generation ................................. ................................................................ .. 7?6 clock feedback modes ........................................................................................................... ............ 7?10 normal mode .................................................................................................................... .............. 7?10 zero delay buffer mode ......................................................................................................... ....... 7?11 no compensation mode ........................................................................................................... .... 7?12 source-synchronous mode ...................................... .................................................................. ... 7?13 hardware features .............................................................................................................. ................ 7?14 clock multiplication & division ................................................................................................ .. 7?14 programmable duty cycle ........................................................................................................ ... 7?15 phase-shifting implementation .................................................................................................. .. 7?16 control signals ................................................................................................................ ................ 7?17 manual clock switchover ........................................................................................................ ..... 7?20 clocking ....................................................................................................................... .............. ........... 7?21 global clock network ........................................................................................................... ........ 7?21 clock control block ............................................................................................................ ........... 7?24 global clock network clock source generation ...................................................................... 7?26 global clock network power down ........................................................................................... 7?28 clkena signals ................................................................................................................. ................. 7?29 board layout ................................................................................................................... .......... ........... 7?30
vi altera corporation cyclone ii device handbook, volume 1 contents vcca & gnda .................................................................................................................... ......... 7?30 vccd & gnd ..................................................................................................................... ............ 7?33 conclusion ..................................................................................................................... ............ ........... 7?33 section iii. memory revision history ............................................................................................................... ..................... 7?1 chapter 8. cyclone ii memory blocks introduction ................................................................................................................... ......................... 8?1 overview ....................................................................................................................... .......................... 8?1 control signals ................................................................................................................ .................. 8?3 parity bit support ............................................................................................................. ................ 8?4 byte enable support ............................................................................................................ ............ 8?4 packed mode support ............................................................................................................ ......... 8?6 address clock enable ........................................................................................................... ........... 8?6 memory modes ................................................................................................................... ................... 8?8 single-port mode ............................................................................................................... ............... 8?9 simple dual-port mode .......................................................................................................... ....... 8?10 true dual-port mode ............................................................................................................ ......... 8?12 shift register mode ............................................................................................................ ............ 8?14 rom mode ....................................................................................................................... ............... 8?16 fifo buffer mode ............................................................................................................... ............ 8?16 clock modes .................................................................................................................... ..................... 8?16 independent clock mode ......................................................................................................... ..... 8?17 input/output clock mode ........................................................................................................ ... 8?19 read/write clock mode .......................................................................................................... ..... 8?22 single-clock mode .............................................................................................................. ........... 8?24 power-up conditions & memory initia lization ........................................................................ 8?27 read-during- write operation at the sa me address ............... ........... ........... ........... ............ ........ 8?28 same-port read-during-write mode .......................................................................................... 8?28 mixed-port read-during-write mode ............................ ............................................................ 8?29 conclusion ..................................................................................................................... ............ ........... 8?30 chapter 9. external memory interfaces introduction ................................................................................................................... ......................... 9?1 external memory interf ace standards ............................................................................................ .... 9?2 ddr & ddr2 sdram ............................................................................................................... ..... 9?2 qdrii sram ..................................................................................................................... ................ 9?5 cyclone ii ddr memory support overview .................................................................................... 9?9 data & data strobe pins .............. .......................................................................................... ........ 9?10 clock, command & address pins ............................................................................................... 9?1 4 parity, dm & ecc pins .......................................................................................................... ....... 9?14 phase lock loop (pll) .......................................................................................................... ........ 9?15 clock delay control ............................................................................................................ ........... 9?15 dqs postamble .................................................................................................................. ............. 9?16
altera corporation vii cyclone ii device handbook, volume 1 contents ddr input registers ............................................................................................................ .......... 9?18 ddr output registers ........................................................................................................... ........ 9?21 bidirectional ddr registers .................................... ................................................................ ..... 9?22 conclusion ..................................................................................................................... ............ ........... 9?24 document revision history ...................................................................................................... ......... 9?25 section iv. i/o standards revision history ............................................................................................................... ..................... 9?1 chapter 10. selectable i/o standards in cyclone ii devices introduction ................................................................................................................... ............ ........... 10?1 supported i/o standards ........................................................................................................ ........... 10?1 3.3-v lvttl (eia/jedec standard jesd8-b) .......................................................................... 10?3 3.3-v lvcmos (eia/jedec standard jesd8-b) .............. ....................................................... 10?4 3.3-v (pci special interest group [sig] pci loca l bus specification revision 3.0) ............. 10?4 3.3-v pci-x .................................................................................................................... .................. 10?6 easy-to-use, low-cost pci express solution ............................................................................ 10?6 2.5-v lvttl (eia/jedec standard eia/ jesd8-5) ................................................................. 10?7 2.5-v lvcmos (eia/jedec standard eia/jesd8-5) ............................................................ 10?7 sstl-2 class i & ii (eia/jedec standard jesd8-9a) ............................................................. 10?7 pseudo-differential sstl-2 .................................... ................................................................. ...... 10?8 1.8-v lvttl (eia/jedec standard eia/ jesd8-7) ................................................................. 10?9 1.8-v lvcmos (eia/jedec standard eia/jesd8-7) ....... ........... ........... ........... ............ ...... 10?10 sstl-18 class i & ii ........................................................................................................... ........... 10?10 1.8-v hstl class i & ii ........................................................................................................ ........ 10?11 pseudo-differential sstl-18 class i & differential ss tl-18 class ii .... ......... ......... ............. 10?12 1.8-v pseudo-differential hstl class i & ii .............. ........... ........... ........... ........... ............ ...... 10?13 1.5-v lvcmos (eia/jedec standard je sd8-11) ................. ........... ........... ............ ........... .... 10?14 1.5-v hstl class i & ii ........................................................................................................ ........ 10?14 1.5-v pseudo-differential hstl class i & ii .............. ........... ........... ........... ........... ............ ...... 10?15 lvds, rsds & mini-lvds ......................................................................................................... 10?16 differential lvpecl ............................................................................................................ ........ 10?17 cyclone ii i/o banks ............................................................................................................ ............ 10?18 programmable current drive strength .......................................................................................... 10 ?24 voltage-referenced i/o standard term ination .......... ........... ........... ........... ............ ........... .... 10?26 differential i/o standard termination ... ................. ........... ........... ........... ......... ......... ............. 10?26 i/o driver impedance matching (r s ) & series termination (r s ) ............ ........... ............ ...... 10?27 pad placement & dc guidelines .................................................................................................. ... 10?27 differential pad placement guid elines ................ ........... ........... ............ ........... ........... ............. 10?28 v ref pad placement guidelines ...... ........... ........... ........... ........... ............ ........... ........... ............. 10?28 dc guidelines .................................................................................................................. ............. 10?32 5.0-v device compatibility ..................................... ................................................................ ......... 10?34 conclusion ..................................................................................................................... ............ ......... 10?36 more information ............................................................................................................... ........... .... 10?37 references ..................................................................................................................... ......... ............. 10?37
viii altera corporation cyclone ii device handbook, volume 1 contents chapter 11. high-speed differential interfaces in cyclone ii devices introduction ................................................................................................................... ............ ........... 11?1 cyclone ii high-speed i/o banks ................................................................................................. ... 11?1 cyclone ii high-speed i/o interface ............................................................................................. .. 11?3 i/o standards support .......................................................................................................... ............. 11?4 lvds standard support in cyclone ii devices ......................................................................... 11?4 rsds i/o standard support in cyclone ii devices ......... ......................................................... 11?7 mini-lvds standard support in cyclone ii devices ....... ......................................................... 11?9 lvpecl support in cyclone ii .................................................................................................. 11 ?11 differential sstl support in cyclone ii devices ......... ........... ........... ........... ............ ........... .... 11?12 differential hstl support in cyclone i i devices ....... ........... ........... ........... ............ ........... .... 11?13 high-speed i/o timing in cyclone ii de vices ............. ........... ........... ........... ......... ......... ............. 11?14 design guidelines .............................................................................................................. ........... .... 11?16 differential pad placement guid elines ................ ........... ........... ............ ........... ........... ............. 11?16 board design considerations .................................................................................................... . 11?16 conclusion ..................................................................................................................... ............ ......... 11?17 section v. dsp revision history ............................................................................................................... ........... ........ 11?1 chapter 12. embedded multipliers in cyclone ii devices introduction ................................................................................................................... ............ ........... 12?1 embedded multiplier block overview ............................................................................................ 1 2?2 architecture ................................................................................................................... ............ ........... 12?4 input registers ................................................................................................................ ................ 12?4 multiplier stage ............................................................................................................... ............... 12?5 output registers ............................................................................................................... .............. 12?6 operational modes .............................................................................................................. ................ 12?6 18-bit multipliers ............................................................................................................. ............... 12?7 9-bit multipliers .............................................................................................................. ................ 12?7 software support ............................................................................................................... .................. 12?9 conclusion ..................................................................................................................... ............ ........... 12?9 section vi. configuration & test revision history ............................................................................................................... ........... ........ 12?1 chapter 13. configuring cyclone ii devices introduction ................................................................................................................... ............ ........... 13?1 cyclone ii configuration overview ............................................................................................... .. 13?1 configuration file format ...................................................................................................... ............ 13?3 configuration data compression .......... ....................................................................................... .... 13?3 active serial configuration (serial configuration devices) .... ........... ........... ........... ............ ........ 13?6 single device as configurat ion ................................................................................................. .. 13?7
altera corporation ix cyclone ii device handbook, volume 1 contents multiple device as configuration .............................. .............................................................. 13? 12 configuring multiple cyclone ii devices with the sa me design ........ ........... ......... ............. 13?15 estimating as configuration time ........................................................................................... 13?1 8 programming serial conf iguration devices ............ ........... ........... ........... ......... ......... ............. 13?19 ps configuration ............................................................................................................... ........... ...... 13?22 single device ps configuration using a max ii device as an exte rnal host ....... ............. 13?22 multiple device ps configuratio n using a max ii device as an ex ternal host ................ 13?26 ps configuration using a microprocesso r ............ ............ ........... ........... ........... ......... ............. 13?31 single device ps configuration us ing a configuration devi ce ........... ........... ......... ............. 13?32 multiple device ps configuration using a configur ation device ...... ........... ......... ............. 13?37 ps configuration using a download ca ble ............. ........... ........... ........... ......... ......... ............. 13?48 jtag configuration ............................................................................................................. ............. 13?53 single device jtag configuration .............................. .............................................................. 13? 55 jtag configuration of multiple devices . ........... ........... ........... ............ ........... ........... ............. 13?58 jam stapl ...................................................................................................................... .............. 13?60 configuring cyclone ii fpgas with jru nner ............ ........... ........... ........... ........... ............ ...... 13?60 combining jtag & active serial conf iguration schemes . ........... ........... ........... ............ ...... 13?61 programming serial conf iguration devices in-system using the jtag interface ............ 13?61 device configuration pins ...................................................................................................... ......... 13?64 conclusion ..................................................................................................................... ............ ......... 13?70 chapter 14. ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices introduction ................................................................................................................... ............ ........... 14?1 ieee std. 1149.1 bst architectu re ........... ........... ............ ........... ........... ........... ......... ......... ......... ...... 14?2 ieee std. 1149.1 boundary-scan register ........ ........... ............ ........... ........... ......... ......... ......... ........ 14?4 boundary-scan cells of a cyclone ii de vice i/o pin ............................................................... 14?4 ieee std. 1149.1 bst operation control .... ........... ........... ........... ........... ........... ........... ............ ....... . 14?6 sample/preload instruction mode ..................................................................................... 14?9 capture phase .................................................................................................................. ............. 14?10 shift & update phases .......................................................................................................... ....... 14?10 extest instruction mode ........................................................................................................ .. 14?11 capture phase .................................................................................................................. ............. 14?12 shift & update phases .......................................................................................................... ....... 14?12 bypass instruction mode ........................................................................................................ .. 14?13 idcode instruction mode ........................................................................................................ . 14?14 usercode instruction mode ................................................................................................... 14? 14 clamp instruction mode ......................................................................................................... . 14?14 highz instruction mode ......................................................................................................... .. 14?15 i/o voltage support in jtag chain ....... ........... ........... ........... ........... ........... ............ ........... .... 14?15 using ieee std. 1149.1 bst circuitry ........................................................................................... .. 14?16 bst for configured devices ..................................................................................................... ........ 14?17 disabling ieee std. 1149.1 bst circuitry ........... ............ ........... ........... ........... ........... ........... ......... 14?18 guidelines for ieee std. 1149.1 boundary -scan testing ...... ........... ........... ........... ......... ............. 14?18 boundary-scan description language (b sdl) support ............. ........... ........... ............ ........... .... 14?19 conclusion ..................................................................................................................... ............ ......... 14?19 references ..................................................................................................................... ......... ............. 14?19 document revision history ...................................................................................................... ....... 14?20
x altera corporation cyclone ii device handbook, volume 1 contents section vii. pcb layout guidelines revision history ............................................................................................................... ........... ........ 14?1 chapter 15. package information for cyclone ii devices introduction ................................................................................................................... ............ ........... 15?1 thermal resistance ............................................................................................................. ........... ...... 15?2 package outlines ............................................................................................................... .................. 15?4 144-pin plastic thin quad flat pack (tqfp) ? wirebond ........................................................ 15?4 208-pin plastic quad flat pack (pqfp) ? wirebond ................................................................. 15?7 240-pin plastic quad flat pack (pqfp) ....................................................................................... 15? 9 256-pin fineline ball -grid array, option 2 ? wire bond ........ ............ ........... ........... ............. 15?11 484-pin fineline bga, option 3 ? wire bond ................ ........... ............ ........... ........... ............. 15?13 484-pin ultra fineline bga ? wirebond .. ............... ........... ........... ........... ......... ......... ............. 15?15 672-pin fineline bga packag e, option 3 ? wirebond .... ........... ........... ........... ......... ............. 15?17 896-pin fineline bga package ? wirebo nd ............ ........... ........... ........... ......... ......... ............. 15?19
altera corporation xi chapter revision dates the chapters in this book, cyclone ii device handbook, volume 1 , were revised on the following dates. where chapters or groups of chapters are av ailable separately, part numbers are listed. chapter 1. introduction revised: february 2007 part number: cii51001-3.1 chapter 2. cyclone ii architecture revised: february 2007 part number: cii51002-3.1 chapter 3. configuration & testing revised: february 2007 part number: cii51003-2.2 chapter 4. hot socketing & power-on reset revised: february 2007 part number: cii51004-3.1 chapter 5. dc characteristic s & timing specifications revised: february 2007 part number: cii51005-3.1 chapter 6. reference & ordering information revised: february 2007 part number: cii51006-1.4 chapter 7. plls in cyclone ii devices revised: february 2007 part number: cii51007-3.1 chapter 8. cyclone ii memory blocks revised: february 2007 part number: cii51008-2.3 chapter 9. external memory interfaces revised: february 2007 part number: cii51009-3.1
xii altera corporation chapter revision dates cyclone ii device handbook, volume 1 chapter 10. selectable i/o stan dards in cyclone ii devices revised: february 2007 part number: cii51010-2.3 chapter 11. high-speed differential interfaces in cyclone ii devices revised: february 2007 part number: cii51011-2.2 chapter 12. embedded multipliers in cyclone ii devices revised: february 2007 part number: cii51012-1.2 chapter 13. configuring cyclone ii devices revised: february 2007 part number: cii51013-3.1 chapter 14. ieee 1149.1 (jtag) boundary -scan testing for cyclone ii devices revised: february 2007 part number: cii51014-2.1 chapter 15. package information for cyclone ii devices revised: february 2007 part number: cii51015-2.3
altera corporation xiii cyclone ii device handbook, volume 1 about this handbook this handbook provides comprehe nsive information about the altera ? cyclone ? ii family of devices. how to contact altera for the most up-to-date information about altera products, go to the altera world-wide web site at www.altera.com . for technical support on this product, go to www.altera.com/mysupport . for additional information about altera products, consult the sources shown below. typographic conventions this document uses the typogr aphic conventions shown below. information type usa & canada all other locations technical support www.altera.com/mysupport/ www.altera.com/mysupport/ (800) 800-epld (3753) (7:00 a.m. to 5:00 p.m. pacific time) +1 408-544-8767 7:00 a.m. to 5:00 p.m. (gmt -8:00) pacific time product literature www.altera.com www.altera.com altera literature services literature@altera.com literature@altera.com non-technical customer service (800) 767-3753 + 1 408-544-7000 7:00 a.m. to 5:00 p.m. (gmt -8:00) pacific time ftp site ftp.altera.com ftp.altera.com visual cue meaning bold type with initial capital letters command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. example: save as dialog box. bold type external timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and softw are utility names are shown in bold type. examples: f max , \qdesigns directory, d: drive, chiptrip.gdf file. italic type with initial capital letters document titles are shown in italic ty pe with initial capital letters. example: an 75: high-speed board design.
xiv altera corporation cyclone ii device handbook, volume 1 typographic conventions italic type internal timing parameters and variables are shown in italic type. examples: t pia , n + 1. variable names are enclosed in angle br ackets (< >) and shown in italic type. example: , .pof file. initial capital letters keyboard keys and menu names ar e shown with initial capital letters. examples: delete key, the options menu. ?subheading title? references to sections within a document and titles of on-line help topics are shown in quotation marks. example: ?typographic conventions.? courier type signal and port names are shown in lowercase courier type. examples: data1 , tdi , input. active-low signals are denoted by suffix n , e.g., resetn . anything that must be typed exactly as it appears is shown in courier type. for example: c:\qdesigns\tutorial\chiptrip.gdf . also, sections of an actual file, such as a report file, refere nces to parts of files (e.g., the ahdl keyword subdesign ), as well as logic function names (e.g., tri ) are shown in courier. 1., 2., 3., and a., b., c., etc. numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. ? bullets are used in a list of items when the sequence of the items is not important. v the checkmark indicates a procedur e that consists of one step only. 1 the hand points to information that requires special attention. c the caution indicates required informati on that needs special consideration and understanding and should be read prior to starting or continuing with the procedure or process. w the warning indicates information that should be read prior to starting or continuing the proce dure or processes r the angled arrow indicates you should press the enter key. f the feet direct you to more information on a particular topic. visual cue meaning
altera corporation section i?1 preliminary section i. cyclone ii device family data sheet this section provides informatio n for board layout designers to successfully layout their boards for cyclone ? ii devices. it contains the required pcb layout guidelines, device pin tables, and package specifications. this section includes the following chapters: chapter 1. introduction chapter 2. cyclone ii architecture chapter 3. configuration & testing chapter 4. hot socketing & power-on reset chapter 5. dc characteristic s & timing specifications chapter 6. reference & ordering information revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the complete handbook.
section i?2 altera corporation preliminary revision history cyclone ii device handbook, volume 1
altera corporation 1?1 february 2007 1. introduction introduction following the immensel y successful first-generation cyclone ? device family, altera ? cyclone ii fpgas extend th e low-cost fpga density range to 68,416 logic elements (les ) and provide up to 622 usable i/o pins and up to 1.1 mbits of embedd ed memory. cyclone ii fpgas are manufactured on 300-mm wafers using tsmc's 90-nm low-k dielectric process to ensure rapid availability and low cost. by minimizing silicon area, cyclone ii devices can support complex digital systems on a single chip at a cost that rivals that of asics. unlike other fpga vendors who compromise power consumption and pe rformance for low-cost, altera?s latest generation of low-cost fpga s?cyclone ii fpgas, offer 60 percent higher performance and half the power consumption of competing 90-nm fpgas. the low cost and op timized feature set of cyclone ii fpgas make them ideal solutions for a wide array of automotive, consumer, communications, video processing, test and measurement, and other end-market solutions. reference designs, system diagrams, and ip, found at www.altera.com , are available to help you rapidly develop complete end-market solutions using cyclone ii fpgas. low-cost embedded processing solutions cyclone ii devices support the nios ii embedded processor which allows you to implement custom-fit embedded processing solutions. cyclone ii devices can also expand the peripheral set, memory, i/o, or performance of embedded processors. single or multiple nios ii embedded processors can be designed into a cyclone ii device to provide additional co-processing power or even replace existing embedded processors in your system. using cyclone ii and nios ii together allow for low-cost, high-performance embedded processi ng solutions which allow you to extend your product's life cycle and improve time to market over standard product solutions. low-cost dsp solutions use cyclone ii fpgas alone or as dsp co-processors to improve price-to-performance ratios for digital signal processing (dsp) applications. you can implement high-performance yet low-cost dsp systems with the following cyclone ii features and design support: up to 150 18 18 multipliers up to 1.1 mbit of on-chip embedded memory high-speed interfaces to external memory cii51001-3.1
1?2 altera corporation cyclone ii device handbook, volume 1 february 2007 features dsp intellectual property (ip) cores dsp builder interface to the ma thworks simulink and matlab design environment dsp development kit, cyclone ii edition cyclone ii devices include a powerful fpga feature set optimized for low-cost applications including a wide range of density, memory, embedded multiplier, and packaging op tions. cyclone ii devices support a wide range of common external me mory interfaces and i/o protocols required in low-cost applications. parameterizable ip cores from altera and partners make using cyclone ii interfaces and protocols fast and easy. features the cyclone ii device family offers the following features: high-density architecture with 4,608 to 68,416 les m4k embedded memory blocks up to 1.1 mbits of ram availabl e without reducing available logic 4,096 memory bits per block (4,6 08 bits per block including 512 parity bits) variable port configurations of 1, 2, 4, 8, 9, 16, 18, 32, and 36 true dual-port (one read and one write, two reads, or two writes) operation for 1, 2, 4, 8, 9, 16, and 18 modes byte enables for data input masking during writes up to 260-mhz operation embedded multipliers up to 150 18- 18-bit multipliers are each configurable as two independent 9- 9-bit multi pliers with up to 250-mhz performance optional input and output registers advanced i/o support high-speed differential i/o standard support, including lvds, rsds, mini-lvds, lvpecl, differential hstl, and differential sstl single-ended i/o standard suppo rt, including 2.5-v and 1.8-v, sstl class i and ii, 1. 8-v and 1.5-v hstl class i and ii, 3.3-v pci and pci-x 1.0, 3.3-, 2.5-, 1.8-, and 1.5-v lvcmos, and 3.3-, 2.5-, and 1.8-v lvttl peripheral component interconnect special interest group (pci sig) pci local bus specification, revision 3.0 compliance for 3.3-v operation at 33 or 66 mhz for 32- or 64-bit interfaces
altera corporation 1?3 february 2007 cyclone ii device handbook, volume 1 introduction pci express with an external ti phy and an altera pci express 1 megacore ? function 133-mhz pci-x 1.0 specification compatibility high-speed external memory support, including ddr, ddr2, and sdr sdram, and qdrii sr am supported by drop in altera ip megacore functions for ease of use three dedicated registers per i/o element (ioe): one input register, one output register, and one output-enable register programmable bus-hold feature programmable output drive strength feature programmable delays from the pin to the ioe or logic array i/o bank grouping for unique vccio and/or vref bank settings multivolt ? i/o standard support for 1.5-, 1.8-, 2.5-, and 3.3- interfaces hot-socketing operation support tri-state with weak pull-up on i/o pins before and during configuration programmable open-drain outputs series on-chip termination support flexible clock management circuitry hierarchical clock network fo r up to 402.5-mhz performance up to four plls per device pr ovide clock multiplication and division, phase shifting, programm able duty cycle, and external clock outputs, allowing system-level clock management and skew control up to 16 global clock lines in th e global clock network that drive throughout the entire device device configuration fast serial configuration allows configuration times less than 100 ms decompression feature allows for smaller programming file storage and faster configuration times supports multiple configuration mo des: active serial, passive serial, and jtag-based configuration supports configuration through lo w-cost serial configuration devices device configuration supports multi ple voltages (either 3.3, 2.5, or 1.8 v) intellectual property altera megafunction and altera megacore function support, and altera megafunctions partners program (ampp sm ) megafunction support, for a wide range of embedded processors, on-chip and off-c hip interfaces, peripheral
1?4 altera corporation cyclone ii device handbook, volume 1 february 2007 features functions, dsp functi ons, and communications functions and protocols. visit the altera ipmegastore at www.altera.com to download ip megacore functions. nios ii embedded processor support the cyclone ii family of fers devices with the fast-on feature, which offers a faster power-on-reset (por) time. devices that support the fast-on feature are designated with an ?a? in the device ordering code. for example, ep2c8a, ep2c15a, and ep2c20a. the ep2c8a and ep2c20a are only available in the in dustrial speed gr ade. the ep2c15a is only available with the fast-on feature and is available in both commercial and industri al grades. the cyclone ii ?a? devices are identical in feature set and function ality to the non-a devices except for support of the faster por time. f for more information on por time specifications for cyclone ii a and non-a devices, refer to the hot socketing & power-on reset chapter in the cyclone ii devi ce handbook . table 1?1 lists the cyclone ii device family features. table 1?2 lists the cyclone ii device package offerings and maximum user i/o pins. table 1?1. cyclone ii fpga family features feature ep2c5 ep2c8 (2) ep2c15 (1) ep2c20 (2) ep2c35 ep2c50 ep2c70 les 4,608 8,256 14,448 18,752 33,216 50,528 68,416 m4k ram blocks (4 kbits plus 512 parity bits 26 36 52 52 105 129 250 total ram bits 119,808 165,888 239,616 239,616 483,840 594,432 1,152,000 embedded multipliers (3) 13 18 26 26 35 86 150 plls 2 2 4 4 4 4 4 maximum user i/o pins 158 182 315 315 475 450 622 notes to ta b l e 1 ? 1 : (1) the ep2c15a is only available with the fast on feature, wh ich offers a faster por time. this device is available in both commercial and industrial grade. (2) the ep2c8 and ep2c20 optionally support the fast on fe ature, which is designated with an ?a? in the device ordering code. the ep2c8a and ep2c20a devices are only available in industrial grade. (3) this is the total number of 18 18 multipliers. for the total number of 9 9 multipliers per device, multiply the total number of 18 18 multipliers by 2.
altera corporation 1?5 february 2007 cyclone ii device handbook, volume 1 introduction cyclone ii devices support vertical migration within the same package (for example, you can migrate between the ep2c35, epc50, and ep2c70 devices in the 672-pin fineline bga pa ckage). the exception to vertical migration support within the cyclone ii family is noted in table 1?3 . table 1?2. cyclone ii package opti ons & maximum user i/o pins notes (1) (2) device 144-pin tqfp (3) 208-pin pqfp (4) 240-pin pqfp 256-pin fineline bga 484-pin fineline bga 484-pin ultra fineline bga 672-pin fineline bga 896-pin fineline bga ep2c5 (6) 89 142 158 (5) ep2c8 (6) 85 138 182 ep2c8a (6) , (7) 182 ep2c15a (6) , (7) 152 315 ep2c20 (6) 142 152 315 ep2c20a (6) , (7) 152 315 ep2c35 (6) 322 322 475 ep2c50 (6) 294 294 450 ep2c70 (6) 422 622 notes to ta b l e 1 ? 2 : (1) cyclone ii devices support vertical migration within the same package (for example, you can migrate between the ep2c20 device in the 484-pin fineline bga ? package and the ep2c35 and ep2c50 devices in the same package). (2) the quartus ? ii software i/o pin counts include four additional pins, tdi , tdo , tms , and tck , which are not available as general purpose i/o pins. (3) tqfp: thin quad flat pack. (4) pqfp: plastic quad flat pack. (5) vertical migration is supported between the ep2c5f256 and the ep2c8f256 devices. however, not all of the dq and dqs groups are supported. vertical migration between the ep2c5 and the ep2c15 in the f256 package is not supported. (6) the i/o pin counts for the ep2c5, ep2c8, and ep2c15a devices include 8 dedicated clock pins that can be used for data inputs. the i/o counts for the ep2c20, ep2c35, ep2c50, and ep2c70 devices include 16 dedicated clock pins that can be used for data inputs. (7) ep2c8a, ep2c15a, and ep2c20a have a fast on feature that has a faster por time. the ep2c15a is only available with the fast on option.
1?6 altera corporation cyclone ii device handbook, volume 1 february 2007 features vertical migration means that yo u can migrate to devices whose dedicated pins, configur ation pins, and power pins are the same for a given package across device densities. 1 when moving from one density to a larger density, i/o pins are often lost because of the greater number of power and ground pins required to support the addi tional logic within the larger device. for i/o pin migration across densities, you must cross reference the available i/o pins us ing the device pin-outs for all planned densities of a given pack age type to identify which i/o pins are migratable. to ensure that your board layout supports migratable densities within one package offering, enable the ap plicable vertical migration path within the quartus ii software (go to assignments menu, then device, then click the migration devices button). after compilation, check the information messages for a full list of i/o, dq, lvds, and other pins that are not available because of the selected migration path. table 1?3 lists the cyclone ii device package offering s and shows the total number of non-migratable i/o pins when migrating from one density device to a larger density device. quartus ii software table 1?3. total number of non-migratable i/o pins for cyclone ii ver tical migration paths vertical migration path 144-pin tqfp 208-pin pqfp 256-pin fineline bga (1) 484-pin fineline bga (2) 484-pin ultra fineline bga 672-pin fineline bga (3) ep2c5 to ep2c8 441 (4) ep2c8 to ep2c15 30 ep2c15 to ep2c20 00 ep2c20 to ep2c35 16 ep2c35 to ep2c50 28 28 (5) 28 ep2c50 to ep2c70 28 28 notes to ta b l e 1 ? 3 : (1) vertical migration between the ep2c5f256 to the ep2c15af256 and the ep2c5f256 to the ep2c20f256 devices is not supported. (2) when migrating from the ep2c20f484 device to the ep2c50 f484 device, a total of 39 i/o pins are non-migratable. (3) when migrating from the ep2c35f672 device to the ep2c70 f672 device, a total of 56 i/o pins are non-migratable. (4) in addition to the one non-migratable i/o pin, there are 34 dq pins that are non-migratable. (5) the pinouts of 484 fbga and 484 ubga are the same.
altera corporation 1?7 february 2007 cyclone ii device handbook, volume 1 introduction cyclone ii devices are available in up to three speed grades: -6, -7, and -8, with -6 being the fastest. table 1?4 shows the cyclone ii device speed-grade offerings. table 1?4. cyclone ii device speed grades device 144-pin tqfp 208-pin pqfp 240-pin pqfp 256-pin fineline bga 484-pin fineline bga 484-pin ultra fineline bga 672-pin fineline bga 896-pin fineline bga ep2c5 - 6, - 7, - 8 - 7, - 8 - 6, - 7, - 8 ep2c8 - 6, - 7, - 8 - 7, - 8 - 6, - 7, - 8 ep2c8a (1) - 8 ep2c15a - 6, - 7, - 8 - 6, - 7, - 8 ep2c20 - 8 - 6, - 7, - 8 - 6, - 7, - 8 ep2c20a (1) - 8 - 8 ep2c35 - 6, - 7, - 8 - 6, - 7, - 8 - 6, - 7, - 8 ep2c50 - 6, - 7, - 8 - 6, - 7, - 8 - 6, - 7, - 8 ep2c70 - 6, - 7, - 8 - 6, - 7, - 8 note to ta b l e 1 ? 4 : (1) ep2c8a and ep2c20a are only available in industrial grade.
1?8 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history document revision history table 1?5 shows the revision history for this document. table 1?5. document revision history date & document version changes made summary of changes february 2007 v3.1 added document revision history. added new note (2) to ta b l e 1 ? 2 . note to explain difference between i/o pin count information provided in table 1?2 and in the quartus ii software documentation. november 2005 v2.1 updated introduction and features. updated table 1?3 . july 2005 v2.0 updated technical content throughout. updated table 1?2 . added tables 1?3 and 1?4 . november 2004 v1.1 updated table 1?2 . updated bullet list in the ?features? section. june 2004 v1.0 added document to the cyclone ii device handbook.
altera corporation 2?1 february 2007 2. cyclone ii architecture functional description cyclone ? ii devices contain a two-dimensional row- and column-based architecture to implement custom lo gic. column and row interconnects of varying speeds provide signal interconnects between logic array blocks (labs), embedded memory blocks, and embedded multipliers. the logic array consists of labs, wi th 16 logic elements (les) in each lab. an le is a small unit of logic providing efficient implementation of user logic functions. labs are grouped into rows and columns across the device. cyclone ii devi ces range in density from 4,608 to 68,416 les. cyclone ii devices provide a global clock network and up to four phase-locked loops (plls). the global clock network consists of up to 16 global clock lines that drive throughout the entire device. the global clock network can provide clocks for all resources within the device, such as input/output elements (ioes), les, embedded multipliers, and embedded memory blocks. the global clock lines can also be used for other high fan-out signals. cyclon e ii plls provide general-purpose clocking with clock synthesis and ph ase shifting as well as external outputs for high-speed differential i/o support. m4k memory blocks are true dual-por t memory blocks wi th 4k bits of memory plus parity (4, 608 bits). these blocks provide dedicated true dual-port, simple dual-port, or sing le-port memory up to 36-bits wide at up to 260 mhz. these blocks are arra nged in columns across the device in between certain labs. cyclone ii devices offer between 119 to 1,152 kbits of embedded memory. each embedded multiplier block can im plement up to either two 9 9-bit multipliers, or one 18 18-bit multiplier with up to 250-mhz performance. embedded multipliers are arranged in columns across the device. each cyclone ii device i/o pin is fed by an ioe located at the ends of lab rows and columns around the peripher y of the device. i/o pins support various single-ended and differential i/o standards, such as the 66- and 33-mhz, 64- and 32-bit pci standard, pci-x, and the lvds i/o standard at a maximum data rate of 805 megabits per second (mbps) for inputs and 640 mbps for outputs. each ioe contains a bidirectional i/o buffer and three registers for registering input, output, and output-enable signals. dual-purpose dqs, dq, and dm pins along with delay chains (used to cii51002-3.1
2?2 altera corporation cyclone ii device handbook, volume 1 february 2007 logic elements phase-align double data rate (ddr) si gnals) provide inte rface support for external memory devices such as ddr, ddr2, and single data rate (sdr) sdram, and qdrii sram devices at up to 167 mhz. figure 2?1 shows a diagram of the cyclone ii ep2c20 device. figure 2?1. cyclone ii ep2c20 device block diagram the number of m4k memory blocks, embedded multiplier blocks, plls, rows, and columns vary per device. logic elements the smallest unit of logic in the cycl one ii architecture, the le, is compact and provides advanced feat ures with efficient logic utilization. each le features: a four-input look-up table (lut), wh ich is a function generator that can implement any functi on of four variables a programmable register a carry chain connection a register chain connection the ability to drive all types of interconnects: local, row, column, register chain, and direct link interconnects support for register packing support for register feedback pll pll ioes pll pll ioes ioes logic array logic array logic array logic array ioes m4k block s m4k blocks embedded multipliers
altera corporation 2?3 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?2 shows a cyclone ii le. figure 2?2. cyclone ii le each le?s programmable register can be configured for d, t, jk, or sr operation. each register has data, clock, clock enable, and clear inputs. signals that use the glob al clock network, genera l-purpose i/o pins, or any internal logic can drive the register?s clock and clear control signals. either general-purpose i/o pins or internal logic can drive the clock enable. for combinational functions, the lut output bypasses the register and drives directly to the le outputs. each le has three outputs that drive the local, row, and column routing resources. the lut or register ou tput can drive these three outputs independently. two le outputs drive column or row and direct link routing connections and one drives local interconnect resources, allowing the lut to drive one output while the register drives another output. this feature, register packing, improves device utilization because the device can use the register and the lut for unrelated functions. when using register packing, the lab-wide synchronous load control signal is not available. see ?lab control signals? on page 2?8 for more information. labclk1 labclk2 labclr2 lab carry-in clock & clock enable select lab carr y -out look-up ta b l e (lut) carry chain row, column, and direct link routing row, column, and direct link routing programmable register clrn d q ena register bypass packed register select chip-wide reset (dev_clrn) labclkena1 labclkena2 synchronous load and clear logic lab-wide synchronous load lab-wide synchronous clear asynchronous clear logic data1 data2 data3 data4 labclr1 local routing register chain output register feedback register chain routing from previous le
2?4 altera corporation cyclone ii device handbook, volume 1 february 2007 logic elements another special packing mode allows the register output to feed back into the lut of the same le so that the re gister is packed with its own fan-out lut, providing another mechanism for improved fitting. the le can also drive out registered and unregistered versions of the lut output. in addition to the three general routing outputs, the les within an lab have register chain outputs. register chain outputs allow registers within the same lab to cascade together. the register chain output allows an lab to use luts for a single combinational function and the registers to be used for an unrelated shift register implementation. these resources speed up connections between labs while saving local interconnect resources. see ?multitrack interconnect? on page 2?10 for more information on register chain connections. le operating modes the cyclone ii le operates in one of the following modes: normal mode arithmetic mode each mode uses le resources differently. in each mode, six available inputs to the le?the four data inputs from the lab local interconnect, the lab carry-in from the previous carry-chain lab, and the register chain connection?are directed to diff erent destinations to implement the desired logic function. lab-wide signals provide clock, asynchronous clear, synchronous clear, synchronous load, and clock enable control for the register. these lab-wide signals are available in all le modes. the quartus ? ii software, in conjunction with parameterized functions such as library of parameterized mo dules (lpm) function s, automatically chooses the appropriate mode for co mmon functions such as counters, adders, subtractors, and arithmetic functions. if required, you can also create special-purpose functions that specify which le operating mode to use for optimal performance. normal mode the normal mode is suitable for general logic applications and combinational functions. in normal mo de, four data inputs from the lab local interconnect are inputs to a four-input lut (see figure 2?3 ). the quartus ii compiler automaticall y selects the carry-in or the data3 signal as one of the inputs to th e lut. les in normal mode support packed registers and register feedback.
altera corporation 2?5 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?3. le in normal mode arithmetic mode the arithmetic mode is ideal for implementing adders, counters, accumulators, and co mparators. an le in arithmetic mode implements a 2-bit full adder and basic carry chain (see figure 2?4 ). les in arithmetic mode can drive out registered and unregistered versions of the lut output. register feedback and regist er packing are supported when les are used in arithmetic mode. data1 four-input lut data2 data3 cin (from cout of previous le) data4 clock (lab wide) ena (lab wide) aclr (lab wide) clrn d q ena sclear (lab wide) sload (lab wide) register chain connection register chain output row, column, and direct link routing row, column, and direct link routing local routing register feedback packed register input
2?6 altera corporation cyclone ii device handbook, volume 1 february 2007 logic elements figure 2?4. le in arithmetic mode the quartus ii compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. parameterized functions such as lpm functions autom atically take advantage of carry chains for the appropriate functions. the quartus ii compiler creates carr y chains longer than 16 les by automatically linking labs in the same column. for enhanced fitting, a long carry chain runs vertically, whic h allows fast horizontal connections to m4k memory blocks or embedded multipliers through direct link interconnects. for example, if a desi gn has a long carry chain in a lab column next to a column of m4k memory blocks, any le output can feed an adjacent m4k memory block thro ugh the direct link interconnect. whereas if the carry chains ran ho rizontally, any lab not next to the column of m4k memory blocks would use other row or column interconnects to drive a m4k memory block. a carry chain continues as far as a full column. clock (lab wide) ena (lab wide) aclr (lab wide) clrn d q ena register chain connection sclear (lab wide) sload (lab wide) register chain output row, column, and direct link routing row, column, and direct link routing local routing register feedback three-input lut three-input lut cin (from cout of previous le) data2 data1 cout
altera corporation 2?7 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture logic array blocks each lab consists of the following: 16 les lab control signals le carry chains register chains local interconnect the local interconnect transfers sign als between les in the same lab. register chain connections transfer the output of one le?s register to the adjacent le?s register within an lab. the quartus ii compiler places associated logic within an lab or adjacent labs, allowing the use of local, and register chain connections for performance and area efficiency. figure 2?5 shows the cyclone ii lab. figure 2?5. cyclone ii lab structure direct link interconnect from adjacen t block direct link interconnect to adjacent block row interconnect column interconnect local interconnect lab direct link interconnect from adjacent block direct link interconnect to adjacent block
2?8 altera corporation cyclone ii device handbook, volume 1 february 2007 logic array blocks lab interconnects the lab local interconnect can drive les within the same lab. the lab local interconnect is driven by column and row interconnects and le outputs within the same lab. neighboring labs, plls, m4k ram blocks, and embedded multi pliers from the left and right can also drive an lab?s local interconnect through th e direct link connection. the direct link connection feature minimi zes the use of row and column interconnects, providing higher performance and flexibility. each le can drive 48 les through fast local and direct link interconnects. figure 2?6 shows the direct link connection. figure 2?6. direct link connection lab control signals each lab contains dedicated logic for driving control signals to its les. the control signals include: two clocks two clock enables two asynchronous clears one synchron ous clear one synchronous load lab direct link interconnect to right direct link interconnect from right lab, m4k memory block, embedded multiplier, pll, or ioe output direct link interconnect from left lab, m4k memory block, embedded multiplier, pll, or ioe output local interconnect direct link interconnect to left
altera corporation 2?9 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture this gives a maximum of seven contro l signals at a time. when using the lab-wide synchronous load, the clkena of labclk1 is not available. additionally, register packing and synchronous load cannot be used simultaneously. each lab can have up to four non-glob al control signals. additional lab control signals can be used as lo ng as they are global signals. synchronous clear and load signals are useful for implementing counters and other functions. the synchronous clear and synchronous load signals are lab-wide signals that affe ct all registers in the lab. each lab can use two clocks and two clock enable signals. each lab?s clock and clock enable signals are linked. for exampl e, any le in a particular lab using the labclk1 signal also uses labclkena1 . if the lab uses both the rising and falling ed ges of a clock, it also uses both lab-wide clock signals. de-asserting the clock enable signal turns off the lab-wide clock. the lab row clocks [5..0] and lab local interconnect generate the lab- wide control signals. the multitrack ? interconnect?s inherent low skew allows clock and control signal di stribution in addition to data. figure 2?7 shows the lab control signal generation circuit. figure 2?7. lab-wide control signals lab-wide signals control the logic for the register?s clear signal. the le directly supports an asynchronous clear function. each lab supports up to two asynchronous clear signals ( labclr1 and labclr2 ). labclkena1 labclk2 labclk1 labclkena2 labclr1 dedicated lab row clocks local interconnect local interconnect local interconnect local interconnect syncload synclr labclr2 6
2?10 altera corporation cyclone ii device handbook, volume 1 february 2007 multitrack interconnect a lab-wide asynchronous load signal to control the logic for the register?s preset signal is not availabl e. the register preset is achieved by using a not gate push-back technique. cyclone ii devices can only support either a preset or asynchronous clear signal. in addition to the clea r port, cyclone ii devices provide a chip-wide reset pin ( dev_clrn ) that resets all registers in th e device. an option set before compilation in the quartus ii software controls this pin. this chip-wide reset overrides all other control signals. multitrack interconnect in the cyclone ii architecture, conne ctions between les, m4k memory blocks, embedded multipliers, and device i/o pins are provided by the multitrack interconnect structure with directdrive? technology. the multitrack interconnect consists of continuous, performance-optimized routing lines of different speeds used for inter- and intra-design block connectivity. the quartus ii compiler automatically places critical paths on faster interconnects to improve design performance. directdrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. the multitrack interconnect and directdrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycl es that typically follow design changes and additions. the multitrack interconnect consists of row (direct link, r4, and r24) and column (register chain, c4, and c 16) interconnects that span fixed distances. a routing structure with fi xed-length resources for all devices allows predictable and repeatable performance when migrating through different device densities. row interconnects dedicated row interconnects route signals to and from labs, plls, m4k memory blocks, and embedded multipliers within the same row. these row resources include: direct link interconnects between labs and adjacent blocks r4 interconnects traversing fo ur blocks to the right or left r24 interconnects for high-speed ac cess across the length of the device
altera corporation 2?11 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture the direct link interconnect allows an lab, m4k memory block, or embedded multiplier block to drive into the local interconnect of its left and right neighbors. only one side of a pll block interfaces with direct link and row interconnects. the direct link interconnect provides fast communication between adjacent labs and/or blocks without using row interconnect resources. the r4 interconnects span four la bs, three labs and one m4k memory block, or three labs and one embedded multiplier to the right or left of a source lab. these resources are used for fast row connections in a four- lab region. every lab has its own set of r4 interconnects to drive either left or right. figure 2?8 shows r4 interconnect connections from an lab. r4 interconnects can drive and be driven by labs, m4k memory blocks, embedded multipliers, plls, and row ioes. for lab interfacing, a primary lab or lab neighbor (see figure 2?8 ) can drive a given r4 interconnect. for r4 interconnects th at drive to the right, the primary lab and right neighbor can drive on to the interconnect. for r4 interconnects that drive to the left, the primary lab and its left neighbor can drive on to the interconnect. r4 interconnects can drive other r4 interconnects to extend the range of labs they can drive. additionally, r4 interconnects can drive r24 interc onnects, c4, and c16 interconnects for connections from one row to another. figure 2?8. r4 interconnect connections notes to figure 2?8 : (1) c4 interconnects can drive r4 interconnects. (2) this pattern is repeated for every lab in the lab row. primary lab (2) r4 interconnect driving left adjacent lab can drive onto another lab's r4 interconnect c4 column interconnects (1) r4 interconnect driving right lab neighbor lab neighbor
2?12 altera corporation cyclone ii device handbook, volume 1 february 2007 multitrack interconnect r24 row interconnects span 24 labs and provide the fastest resource for long row connections between non-ad jacent labs, m4k memory blocks, dedicated multipliers, and row ioes. r24 row interconnects drive to other row or column interconnects at every fourth lab. r24 row interconnects drive lab local interconnects via r4 and c4 interconnects and do not drive directly to lab local interconnects. r24 interconnects can drive r24, r4, c16, and c4 interconnects. column interconnects the column interconnect operates similar to the row interconnect. each column of labs is served by a dedicated column interconnect, which vertically routes signals to and from labs, m4k memory blocks, embedded multipliers, and row and column ioes. these column resources include: register chain intercon nects within an lab c4 interconnects traversing a distan ce of four blocks in an up and down direction c16 interconnects for high-speed vertical routing through the device cyclone ii devices include an enhanc ed interconnect structure within labs for routing le output to le input connections faster using register chain connections. the register chai n connection allows the register output of one le to connect directly to the register input of the next le in the lab for fast shift registers. th e quartus ii compiler automatically takes advantage of these resources to improve utilization and performance. figure 2?9 shows the register chain interconnects.
altera corporation 2?13 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?9. register chain interconnects the c4 interconnects span four labs, m4k blocks, or embedded multipliers up or down from a source lab. every lab has its own set of c4 interconnects to drive either up or down. figure 2?10 shows the c4 interconnect connections from an lab in a column. the c4 interconnects can drive and be driven by all types of architecture blocks, including plls, m4k memory blocks, embedded multiplier blocks, and column and row ioes. for lab interconnection, a primary lab or its lab neighbor (see figure 2?10 ) can drive a given c4 interconnect. c4 interconnects can drive each other to extend their range as well as drive row interconnects for colu mn-to-column connections. le 1 le 2 le 3 le 4 le 5 le 6 le 7 le 8 le 9 le 10 le 11 le 12 le13 le 14 le 15 le 16 carry chain routing to adjacent le local interconnect register chain routing to adjacen t le's register input local interconnect routing among les in the lab
2?14 altera corporation cyclone ii device handbook, volume 1 february 2007 multitrack interconnect figure 2?10. c4 inte rconnect connections note (1) note to figure 2?10 : (1) each c4 interconnect can drive either up or down four rows. c4 interconnect drives local and r 4 interconnects up to four rows adjacent lab can drive onto neighboring lab's c4 interconnect c4 interconnect driving up c4 interconnect driving down lab row interconnect local interconnect primary lab lab neighbor
altera corporation 2?15 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture c16 column interconnects span a length of 16 labs and provide the fastest resource for long column connections between labs, m4k memory blocks, embedded multipliers, and ioes. c16 column interconnects drive to other row and column interconnects at every fourth lab. c16 column interconnects drive lab local interconnects via c4 and r4 interconnects and do not drive lab local interconnects directly. c16 interconnects can drive r24, r4, c16, and c4 interconnects. device routing all embedded blocks communicate with the logic array similar to lab-to-lab interfaces. each block (for example, m4k memory, embedded multiplier, or pll) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. these bloc ks also have direct link interconnects for fast connections to and from a neighboring lab. table 2?1 shows the cyclone ii device?s routing scheme. table 2?1. cyclone ii device routing scheme (part 1 of 2) source destination register chain local interconnect direct link interconnect r4 interconnect r24 interconnect c4 interconnect c16 interconnect le m4k ram block embedded multiplier pll column ioe row ioe register chain v local interconnect vvvvvv direct link interconnect v r4 interconnect v vvvv r24 interconnect vvvv c4 interconnect v vvvv c16 interconnect vvvv
2?16 altera corporation cyclone ii device handbook, volume 1 february 2007 global clock network & phase-locked loops global clock network & phase-locked loops cyclone ii devices provide global clock networks and up to four plls for a complete clock management solution . cyclone ii clock network features include: up to 16 global clock networks up to four plls global clock network dynamic clock source selection global clock network dynamic enable and disable le vvvv v m4k memory block vvv v embedded multipliers vvv v pll vv v column ioe vv row ioe vvvv table 2?1. cyclone ii device routing scheme (part 2 of 2) source destination register chain local interconnect direct link interconnect r4 interconnect r24 interconnect c4 interconnect c16 interconnect le m4k ram block embedded multiplier pll column ioe row ioe
altera corporation 2?17 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture each global clock network has a cl ock control block to select from a number of input clock sources (pll clock outputs, clk[] pins, dpclk[] pins, and internal logic) to driv e onto the global clock network. table 2?2 lists how many plls, clk[] pins, dpclk[] pins, and global clock networks are available in each cyclone ii device. clk[] pins are dedicated clock pins and dpclk[] pins are dual-purpose clock pins. figures 2?11 and 2?12 show the location of the cyclone ii plls, clk[] inputs, dpclk[] pins, and clock control blocks. table 2?2. cyclone ii device clock resources device number of plls number of clk pins number of dpclk pins number of global clock networks ep2c5 2 8 8 8 ep2c8 2 8 8 8 ep2c15 4 16 20 16 ep2c20 4 16 20 16 ep2c35 4 16 20 16 ep2c50 4 16 20 16 ep2c70 4 16 20 16
2?18 altera corporation cyclone ii device handbook, volume 1 february 2007 global clock network & phase-locked loops figure 2?11. ep2c5 & ep2c8 pll, clk[], d pclk[] & clock control block locations note to figure 2?11 : (1) there are four clock control blocks on each side. pll 2 clk[7..4] dpclk7 dpclk6 clk[3..0] dpclk0 dpclk1 dpclk10 dpclk8 dpclk2 gclk[7..0] gclk[7..0] dpclk4 pll 1 8 8 8 8 clock control block (1) clock control block (1) 4 4 4 4
altera corporation 2?19 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?12. ep2c15 & larger pll, clk[], d pclk[] & clock control block locations notes to figure 2?12 : (1) there are four clock control blocks on each side. (2) only one of the corner cdpclk pins in each corner can feed the clock control block at a time. the other cdpclk pins can be used as general-purpose i/o pins. pll 4 pll 3 pll 2 clk[7..4] dpclk7 cdpclk5 cdpclk4 dpclk6 clk[3..0] dpclk0 cdpclk0 cdpclk1 dpclk1 cdpclk7 dpclk[9..8] dpclk[11..10] clk[11..8] gclk[15..0] gclk[15..0] pll 1 cdpclk6 cdpclk2 dpclk[5..4] dpclk[3..2] clk[15..12] cdpclk3 clock control block (1) clock control block (1) 16 16 16 16 22 4 4 4 4 4 2 2 4 (2) (2) (2) (2) 4 4 3 3 3 3
2?20 altera corporation cyclone ii device handbook, volume 1 february 2007 global clock network & phase-locked loops dedicated clock pins larger cyclone ii devices (ep2c15 and larger devices) have 16 dedicated clock pins ( clk[15..0] , four pins on each side of the device). smaller cyclone ii devices (ep2c5 and ep2c8 devices) have eight dedicated clock pins ( clk[7..0] , four pins on left and right sides of the device). these clk pins drive the global clock network (gclk), as shown in figures 2?11 and 2?12 . if the dedicated clock pins are not us ed to feed the glob al clock networks, they can be used as general-purpose input pins to feed the logic array using the multitrack interconnect. howe ver, if they are used as general- purpose input pins, they do not have support for an i/o register and must use le-based registers in place of an i/o register. dual-purpose clock pins cyclone ii devices have either 20 dual-purpose clock pins, dpclk[19..0] or 8 dual-purpose clock pins, dpclk[7..0] . in the larger cyclone ii devices (ep2c15 devices and higher), there are 20 dpclk pins; four on the left and right sides and six on the top and bottom of the device. the corner cdpclk pins are first multiplexed before they drive into the clock control bloc k. since the signals pass through a multiplexer before feeding the clock control block, these signals incur more delay to the clock control block than other dpclk pins that directly feed the clock control block. in the smaller cyclone ii devices (ep2c5 and ep2c8 devices), there are eight dpclk pins; two on each side of the device (see figures 2?11 and 2?12 ). a programmable delay chain is available from the dpclk pin to its fan- out destinations. to set the propagation delay from the dpclk pin to its fan-out destinations, use the input delay from dual-purpose clock pin to fan-out destinations assignment in the quartus ii software. these dual-purpose pins can connect to the global clock network for high-fanout control signals such as clocks, asynchronous clears, presets, and clock enables, or protocol control signals such as trdy and irdy for pci, or dqs signals for ex ternal memory interfaces.
altera corporation 2?21 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture global clock network the 16 or 8 global clock networks drive throughout the entire device. dedicated clock pins ( clk[] ), pll outputs, the logic array, and dual-purpose clock ( dpclk[] ) pins can also driv e the global clock network. the global clock network can provide clocks for all resources within the device, such as ioes, les, memory blocks, and embedded multipliers. the global clock lines can also be used for control signals, such as clock enables and synchronous or asynchrono us clears fed from the external pin, or dqs signals for ddr sdram or qdrii sram interfaces. internal logic can also drive the global cloc k network for internally generated global clocks and asynchronous clea rs, clock enables, or other control signals with large fan-out. clock control block there is a clock control block for each global clock netw ork available in cyclone ii devices. the clock control blocks are arranged on the device periphery and there are a maximum of 16 clock control blocks available per cyclone ii device. the larger cyclone ii devices (ep2c15 devices and larger) have 16 clock control blocks, four on each side of the device. the smaller cyclone ii devices (ep2c5 and ep2c8 devices) have eight clock control blocks, four on the left and right sides of the device. the control block has these functions: dynamic global clock network clock source selection dynamic enable/disable of the global clock network in cyclone ii devices, the dedicated clk[] pins, pll counter outputs, dpclk[] pins, and internal logic can all feed the clock control block. the output from the clock control bloc k in turn feeds the corresponding global clock network. the following sources can be inputs to a given clock control block: four clock pins on the same si de as the clock control block three pll clock outputs from a pll four dpclk pins (including cdpclk pins) on the same side as the clock control block four internally-generated signals
2?22 altera corporation cyclone ii device handbook, volume 1 february 2007 global clock network & phase-locked loops of the sources listed, only two cloc k pins, two pll clock outputs, one dpclk pin, and one internally-generated signal are chosen to drive into a clock control block. figure 2?13 shows a more detailed diagram of the clock control block. out of these six inputs, the two clock input pins and two pll outputs can be dynamic select ed to feed a global clock network. the clock control block supports static selection of dpclk and the signal from internal logic. figure 2?13. clock control block notes to figure 2?13 : (1) the clkswitch signal can either be set through the configuration file or it can be dynamically set when using the manual pll switchover feature. the output of the multiplexer is the input reference clock (f in ) for the pll. (2) the clkselect[1..0] signals are fed by internal logic and can be used to dynamically select the clock source for the global clock network when the device is in user mode. (3) the static clock select signals are se t in the configuration file and cannot be dynamically controlled when the device is in user mode. (4) internal logic can be used to enabled or di sabled the global clock network in user mode. clkswitch (1) static clock select (3) static clock select (3) internal logic clock control block dpclk or cdpclk clkselect[1..0] (2) clkena (4) inclk1 inclk0 clk[ n + 3] clk[ n + 2] clk[ n + 1] clk[ n ] f in c0 c1 c2 pll global clock enable/ disable (3)
altera corporation 2?23 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture global clock network distribution cyclone ii devices contains 16 global clock networks. the device uses multiplexers with these cl ocks to form six-bit buses to drive column ioe clocks, lab row clocks, or row ioe clocks (see figure 2?14 ). another multiplexer at the lab level selects tw o of the six lab row clocks to feed the le registers within the lab. figure 2?14. global clock network multiplexers lab row clocks can feed les, m4k memory blocks, and embedded multipliers. the lab row clocks also extend to the row i/o clock regions. ioe clocks are associated with row or column bl ock regions. only six global clock resources feed to these row and column regions. figure 2?15 shows the i/o clock regions. clock [15 or 7..0] row i/o region io_clk [5..0] column i/o region io_clk [5..0] lab row clock labclk[5..0] global clock network
2?24 altera corporation cyclone ii device handbook, volume 1 february 2007 global clock network & phase-locked loops figure 2?15. lab & i/o clock regions f for more information on the global clock network and the clock control block, see the plls in cyclone ii devices chapter in volume 1 of the cyclone ii devi ce handbook . column i/o clock region io_clk[5..0] column i/o clock region io_clk[5..0] 6 6 i/o clock regions i/o clock regions 8 or 16 global clock network row i/o cloc k region io_clk[5..0] cyclone logic array 6 6 lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] 6 6 6 6 6 6 6 6 6 6
altera corporation 2?25 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture plls cyclone ii plls provide general-purpos e clocking as well as support for the following features: clock multiplication and division phase shifting programmable duty cycle up to three internal clock outputs one dedicated external clock output clock outputs for differential i/o support manual clock switchover gated lock signal three different clock feedback modes control signals cyclone ii devices contain either two or four plls. table 2?3 shows the plls available for each cyclone ii device. table 2?3. cyclone ii device pll availability device pll1 pll2 pll3 pll4 ep2c5 vv ep2c8 vv ep2c15 vvvv ep2c20 vvvv ep2c35 vvvv ep2c50 vvvv ep2c70 vvvv
2?26 altera corporation cyclone ii device handbook, volume 1 february 2007 global clock network & phase-locked loops table 2?4 describes the pll features in cyclone ii devices. table 2?4. cyclone ii pll features feature description clock multiplication and division m / ( n post-scale counter) m and post-scale counter values (c0 to c2) range from 1 to 32. n ranges from 1 to 4. phase shift cyclone ii plls have an advan ced clock shift capability that enables programmable phase shifts in increments of at least 45. the finest resolution of phase shifting is determi ned by the voltage control oscillator (vco) period divided by 8 (for example, 1/1000 mhz/8 = down to 125-ps increments). programmable duty cycle the programmable duty cycl e allows plls to generate clock outputs with a variable duty cycle. this feature is supported on each pll post-scale counter (c0-c2). number of internal clock outputs the cyclone ii pll has three outputs which can drive the global clock network. one of these outputs (c2) can also drive a dedicated pll < # > _out pin (single ended or differential). number of external clock outputs the c2 output drives a dedicated pll < # > _out pin. if the c2 output is not used to drive an external clock output, it can be used to drive the internal global clock network. the c2 output can concurrently drive the external clock output and internal global clock network. manual clock switchover the cyclone ii plls suppor t manual switchover of the reference clock through internal logic. this enables you to switch between two reference input clocks during user mode for appl ications that may require clock redundancy or support for clocks with two different frequencies. gated lock signal the lock output indicates that there is a stable clock output signal in phase with the reference clock. cyclone ii plls include a programmable counter that holds the lock signal low for a user-selected number of input clock transitions, allowing the pll to lock before enabling the locked signal. either a gated locked signal or an ungated locked signal from the locked port can drive internal logic or an output pin. clock feedback modes in zero delay buffer mode , the external clock output pin is phase-aligned with the clock input pin for zero delay. in normal mode, the pll compensates for the internal global clock network delay from the input clock pin to the clock port of the ioe output registers or registers in the logic array. in no compensation mode, the pll does not compensate for any clock networks. control signals the pllenable signal enables and disables the plls. the areset signal resets/resynchronizes the inputs for each pll. the pfdena signal controls the phase frequency detector (pfd) output with a programmable gate.
altera corporation 2?27 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?16 shows a block diagram of the cyclone ii pll. figure 2?16. cyclone ii pll note (1) notes to figure 2?16 : (1) this input can be single-ended or differential. if you are using a differential i/o standard, then two clk pins are used. lvds input is supported via the secondary function of the dedicated clk pins. for example, the clk0 pin?s secondary function is lvdsclk1p and the clk1 pin?s secondary function is lvdsclk1n . if a differential i/o standard is assigned to the pll clock input pin, the corresponding clk(n) pin is also completely used. the figure 2?16 shows the possible clock input connections ( clk0 / clk1 ) to pll1. (2) this counter output is shared between a dedicated external clock output i/o and the global clock network. f for more information on cyclone ii plls, see the plls in the cyclone ii devices chapter in volume 1 of the cyclone ii device handbook . embedded memory the cyclone ii embedded memory cons ists of columns of m4k memory blocks. the m4k memory bl ocks include input regi sters that synchronize writes and output registers to pipeline designs and improve system performance. the output registers can be bypassed, but input registers cannot. pfd loop filter lock detect & filter vco charge pump c0 c1 c2 m n global clock global clock global clock to i/o or general routing pll< # >_out post-scale counters vco phase selection selectable at each pll output port clk1 clk3 clk2 (1) clk0 (1) inclk0 inclk1 up down 8 8 8 f vco f fb f in reference input clock f ref = f in / n (2) manual clock switchover select signal k (3)
2?28 altera corporation cyclone ii device handbook, volume 1 february 2007 embedded memory each m4k block can implement various types of memory with or without parity, including true dual-port, simp le dual-port, and single-port ram, rom, and first-in first-out (fifo) buffers. the m4k blocks support the following features: 4,608 ram bits 250-mhz performance true dual-port memory simple dual-port memory single-port memory byte enable parity bits shift register fifo buffer rom various clock modes address clock enable 1 violating the setup or hold time on the memory block address registers could corrupt memory contents. this applies to both read and write operations. table 2?5 shows the capacity and distribut ion of the m4k memory blocks in each cyclone ii device. table 2?5. m4k memory capacity & distribution in cyclone ii devices device m4k columns m4k blocks total ram bits ep2c5 2 26 119,808 ep2c8 2 36 165,888 ep2c15 2 52 239,616 ep2c20 2 52 239,616 ep2c35 3 105 483,840 ep2c50 3 129 594,432 ep2c70 5 250 1,152,000
altera corporation 2?29 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture table 2?6 summarizes the features supported by the m4k memory. table 2?6. m4k memory features feature description maximum performance (1) 250 mhz total ram bits per m4k block (including parity bits) 4,608 configurations supported 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 (not available in true dual-port mode) 128 36 (not available in true dual-port mode) parity bits one parity bit for each byte. the parity bit, along with internal user logic, can implement parity checking for error detection to ensure data integrity. byte enable m4k blocks support byte writes when the write port has a data width of 1, 2, 4, 8, 9, 16, 18, 32, or 36 bits. the byte enables allow the input data to be masked so the device can write to specific bytes. the unwritten bytes retain the previous written value. packed mode two single-port memory blocks can be packed into a single m4k block if each of the two independent block sizes are equal to or less than half of the m4k block size, and each of the single -port memory blocks is configured in si ngle-clock mode. address clock enable m4k blocks s upport address clock enable, which is used to hold the previous addr ess value for as long as the signal is enabled. this f eature is useful in handling misses in cache applications. memory initialization file ( .mif ) when configured as ram or rom, you can use an initialization file to pre-load the memory contents. power-up condition outputs cleared register clears out put registers only same-port read-during-write new dat a available at positive clock edge mixed-port read-during-wr ite old data available at positive clock edge note to ta b l e 2 ? 6 : (1) maximum performance information is pr eliminary until device characterization.
2?30 altera corporation cyclone ii device handbook, volume 1 february 2007 embedded memory memory modes table 2?7 summarizes the different memory modes supported by the m4k memory blocks. 1 embedded memory can be inferred in your hdl code or directly instantiated in the quartus ii software using the megawizard ? plug-in manager memory compiler feature. table 2?7. m4k memory modes memory mode description single-port memory m4k blocks suppo rt single-port mode, used when simultaneous reads and writes are not required. single-port memory supports non-simultaneous reads and writes. simple dual-port memory simple dual-port memory supports a simultaneous read and write. simple dual-port with mixed width simple dual-port memory mode with different read and write port widths. true dual-port memory true dual-port mode supports any combination of two-port operations: two r eads, two writes, or one read and one write at two different clock frequencies. true dual-port with mixed width true dual-port mode with different read and write port widths. embedded shift register m4k memory bloc ks are used to implement shift registers. data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. rom the m4k memory blocks support rom mode. a mif initializes the rom contents of these blocks. fifo buffers a single clock or dual clock fifo may be implemented in the m4k blocks. simultaneous read and write from an empty fifo buffer is not supported.
altera corporation 2?31 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture clock modes table 2?8 summarizes the different cloc k modes supported by the m4k memory. table 2?9 shows which clock modes are supported by all m4k blocks when configured in the different memory modes. m4k routing interface the r4, c4, and direct link interconnects from adjacent labs drive the m4k block local interconnect. the m4k blocks can communicate with labs on either the left or right side through these row resources or with lab columns on either the right or left with the column resources. up to 16 direct link input connections to the m4k block are possible from the left adjacent lab and another 16 possible from the right adjacent lab. m4k block outputs can also connect to left and right labs through each 16 direct link interconnects. figure 2?17 shows the m4k block to logic array interface. table 2?8. m4k clock modes clock mode description independent in this mode, a separate clock is available for each port (ports a and b). clock a controls all registers on the port a side, while clock b controls all regi sters on the port b side. input/output on each of the two ports, a or b, one clock controls all registers for inputs into the memory block: data input, wren , and address. the other clock controls the block?s data output registers. read/write up to two clocks are available in this mode. the write clock controls the block?s data inputs, wraddress , and wren . the read clock controls the data output, rdaddress , and rden . single in this mode, a single clock, together with clock enable, is used to control all registers of the memory block. asynchronous clear signals for the registers are not supported. table 2?9. cyclone ii m4k memory clock modes clocking modes true dual-port mode simple dual-port mode single-port mode independent v input/output vvv read/write v single clock vvv
2?32 altera corporation cyclone ii device handbook, volume 1 february 2007 embedded multipliers figure 2?17. m4k ram block lab row interface f for more information on cyclone ii embedded memory, see the cyclone ii memory blocks chapter in volume 1 of the cyclone ii device handbook . embedded multipliers cyclone ii devices have embedded multiplier blocks optimized for multiplier-intensive digital signal pr ocessing (dsp) func tions, such as finite impulse response (fir) filt ers, fast fourier transform (fft) functions, and discrete cosine transf orm (dct) functions. you can use the embedded multiplier in one of two basic operational modes, depending on the application needs: one 18-bit multiplier up to two independent 9-bit multipliers dataout m4k ram block datain address 16 16 16 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m4k ram block local interconnect region c4 interconnects r4 interconnects lab row clocks clocks byte enable control signals 6
altera corporation 2?33 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture embedded multipliers can operate at up to 250 mhz (for the fastest speed grade) for 18 18 and 9 9 multiplic ations when using both input and output registers. each cyclone ii device has one to three columns of embedded multipliers that efficiently implement multipli cation functions. an embedded multiplier spans the height of one lab row. table 2?10 shows the number of embedded multipliers in each cyclone ii device and the multipliers that can be implemented. the embedded multiplier consis ts of the following elements: multiplier block input and output registers input and output interfaces figure 2?18 shows the multiplier block architecture. table 2?10. number of embedded mult ipliers in cyclone ii devices note (1) device embedded multiplier columns embedded multipliers 9 9 multipliers 18 18 multipliers ep2c5 1 13 26 13 ep2c8 1 18 36 18 ep2c15 1 26 52 26 ep2c20 1 26 52 26 ep2c35 1 35 70 35 ep2c50 2 86 172 86 ep2c70 3 150 300 150 note to table 2?10 : (1) each device has either the number of 9 9-, or 18 18-bit multipliers shown . the total number of multipliers for each device is not the sum of all the multipliers.
2?34 altera corporation cyclone ii device handbook, volume 1 february 2007 embedded multipliers figure 2?18. multiplier block architecture note to figure 2?18 : (1) if necessary, these signals can be registered once to match the data signal path. each multiplier operand can be a un ique signed or unsigned number. two signals, signa and signb , control the representation of each operand respectively. a logic 1 value on the signa signal indicates that data a is a signed number while a logic 0 value indicates an unsigned number. table 2?11 shows the sign of the multiplication result for the various operand sign repres entations. the result of the multiplication is signed if any one of the operands is a signed value. clrn dq ena data a data b aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena data out embedded multiplier block output register input register table 2?11. multiplier sign representation data a (signa value) data b (signb value) result unsigned unsigned unsigned unsigned signed signed signed unsigned signed signed signed signed
altera corporation 2?35 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture there is only one signa and one signb signal for each dedicated multiplier. therefore, all of the data a inputs feeding the same dedicated multiplier must have the same sign re presentation. similarly, all of the data b inputs feeding the same dedicated multiplier must have the same sign representation. the signa and signb signals can be changed dynamically to modify the sign repres entation of the in put operands at run time. the multiplier offers full precision regardless of the sign representation and can be registered using dedicated registers located at the input register stage. multiplier modes table 2?12 summarizes the different modes that the embedded multipliers can operate in. table 2?12. embedded multiplier modes multiplier mode description 18-bit multiplier an embedded multiplier can be configured to support a single 18 18 multiplier for operand widths up to 18 bits. all 18-bit multiplier inputs and results can be registered independently. the multiplier operands can accept signed integers, unsigned integers, or a combination of both. 9-bit multiplier an embedded multipli er can be configured to support two 9 9 independent multipliers for operand widths up to 9-bits. both 9-bit multiplier inputs and results can be registered independently. the multiplier operands can accept signed integers, unsigned integers or a combination of both. there is only one signa signal to control the sign representation of both data a inputs and one signb signal to control the sign representation of both data b inputs of the 9-bit multipliers within the same dedicated multiplier.
2?36 altera corporation cyclone ii device handbook, volume 1 february 2007 embedded multipliers embedded multiplier routing interface the r4, c4, and direct link interconnects from adjacent labs drive the embedded multiplier row interface interconnect. the embedded multipliers can communicate with labs on either the left or right side through these row resources or with lab columns on either the right or left with the column resources. up to 16 direct link input connections to the embedded multiplier are possible from the left adjacent labs and another 16 possible from the right adjacent lab. embedded multiplier outputs can also connect to left and right labs through 18 direct link interconnects each. figure 2?19 shows the embedded multiplier to logic array interface. figure 2?19. embedded multiplier lab row interface lab lab row interface block embedded multiplier 16 [35..0] [35..0] embedded multiplier to lab row interface block interconnect region 36 inputs per row 36 outputs per row r4 interconnects c4 interconnects c4 interconnects direct link interconnect from adjacent lab 18 direct link outputs to adjacent labs direct link interconnect from adjacent lab 18 18 36 36 control 5 18 18 16 lab block interconect region lab block interconect region
altera corporation 2?37 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture there are five dynamic control inpu t signals that feed the embedded multiplier: signa , signb , clk , clkena , and aclr . signa and signb can be registered to match the data signal input path. the same clk , clkena , and aclr signals feed all registers within a single embedded multiplier. f for more information on cyclone ii embedded multipliers, see the embedded multipliers in cyclone ii devices chapter. i/o structure & features ioes support many features, including: differential and single-ended i/o standards 3.3-v, 64- and 32-bit, 66- and 33-mhz pci compliance joint test action group (jtag) boundary-scan test (bst) support output drive strength control weak pull-up resistors during configuration tri-state buffers bus-hold circuitry programmable pull-up resistors in user mode programmable input and output delays open-drain outputs dq and dqs i/o pins v ref pins cyclone ii device ioes contain a bidirectional i/o buffer and three registers for complete embedded bidirectional single data rate transfer. figure 2?20 shows the cyclone ii ioe structure. the ioe contains one input register, one output register, and one output enable register. you can use the input registers for fast setup times and output registers for fast clock-to-output times. additionally, you can use the output enable (oe) register for fast clock-to-output enable timing. the quartus ii software automatically duplicates a single oe register that controls multiple output or bidirectional pins. you ca n use ioes as input, output, or bidirectional pins.
2?38 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o structure & features figure 2?20. cyclone ii ioe structure note to figure 2?20 : (1) there are two paths available for combinational or registered inputs to the logic array. each path contains a unique programmable delay chain. the ioes are located in i/o blocks ar ound the periphery of the cyclone ii device. there are up to five ioes per row i/o block and up to four ioes per column i/o block (column i/o blocks span two columns). the row i/o blocks drive row, column (only c4 interconnects), or direct link interconnects. the column i/o blocks drive column interconnects. figure 2?21 shows how a row i/o block connects to the logic array. figure 2?22 shows how a column i/o bloc k connects to th e logic array. output register output input (1) oe register oe input register logic array
altera corporation 2?39 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?21. row i/o block c onnection to the interconnect notes to figure 2?21 : (1) the 35 data and control signals consist of five data out lines, io_dataout[4..0] , five output enables, io_coe[4..0] , five input clock enables, io_cce_in[4..0] , five output clock enables, io_cce_out[4..0] , five clocks, io_cclk[4..0] , five asynchronous clear signals, io_caclr[4..0] , and five synchronous clear signals, io_csclr[4..0] . (2) each of the five ioes in the row i/o block can have two io_datain (combinational or registered) inputs. 35 r4 & r24 interconnects c4 interconnects i/o block local interconnect 35 data and control signals from logic array (1 ) io_datain0[4..0] io_datain1[4..0] (2) io_clk[5..0] row i/o block contains up to five ioes direct link interconnect to adjacent lab direct link interconnect from adjacent lab lab local interconnect lab row i/o block
2?40 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o structure & features figure 2?22. column i/o block connection to the interconnect notes to figure 2?22 : (1) the 28 data and control signals consist of four data out lines, io_dataout[3..0] , four output enables, io_coe[3..0] , four input clock enables, io_cce_in[3..0] , four output clock enables, io_cce_out[3..0] , four clocks, io_cclk[3..0] , four asynchronous clear signals, io_caclr[3..0] , and four synchronous clear signals, io_csclr[3..0] . (2) each of the four ioes in the column i/o block can have two io_datain (combinational or registered) inputs. 28 data & control signals from logic array (1) column i/o block contains up to four ioe s i/o block local interconnect io_datain0[3..0] io_datain1[3..0] (2) r4 & r24 interconnects lab local interconnect c4 & c24 interconnects 28 lab lab lab io_clk[5..0] column i/o block
altera corporation 2?41 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture the pin?s datain signals can drive the logic array. the logic array drives the control and data signals, providing a flexible routing resource. the row or column ioe clocks, io_clk[5..0] , provide a dedicated routing resource for low-skew, high-speed clocks. the global clock network generates the ioe clocks that feed the row or column i/o regions (see ?global clock network & phase-locked loops? on page 2?16 ). figure 2?23 illustrates the signal pa ths through the i/o block. figure 2?23. signal path through the i/o block each ioe contains its own control signal selection for the following control signals: oe , ce_in , ce_out , aclr / preset , sclr / preset , clk_in , and clk_out . figure 2?24 illustrates the control signal selection. row or column io_clk[5..0] io_datain0 io_datain1 io_dataout io_coe oe ce_in ce_out io_cce_in aclr/preset io_cce_out sclr/preset io_caclr clk_in io_cclk clk_out dataout data and control signal selection ioe to logic array from logic array to other ioes io_csclr
2?42 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o structure & features figure 2?24. control signal selection per ioe in normal bidirectional operation, you can use the input register for input data requiring fast setup times. the input register can have its own clock input and clock enable separate from the oe and output registers. you can use the output register for data requiring fast clock-to-output performance. the oe register is available for fast clock-to-output enable timing. the oe and output register share the same clock source and the same clock enable source from the lo cal interconnect in the associated lab, dedicated i/o clocks, or the column and row interconnects. all registers share sclr and aclr , but each register can individually disable sclr and aclr . figure 2?25 shows the ioe in bidirectional configuration. clk_out ce_in clk_in ce_out aclr/preset sclr/preset dedicated i/o clock [5..0] local interconnect local interconnect local interconnect local interconnect local interconnect oe io_coe io_caclr local interconnect io_csclr io_cce_out io_cce_in io_cclk
altera corporation 2?43 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?25. cyclone ii ioe in bidi rectional i/o configuration the cyclone ii device ioe includes programmable delays to ensure zero hold times, minimi ze setup times, or increa se clock to output times. a path in which a pin directly drives a register may require a programmable delay to ensure zero hold time, whereas a path in which a pin drives a register through combinational logic may not require the delay. programmable delays decrea se input-pin-to-logic-array and ioe input register delays. the quartus ii compiler can program these delays to automatically minimize setup time while providing a zero hold time. chip- w ide reset oe register v ccio optio n al pci clamp col u mn or ro w interconect io_clk[5..0] inp u t register inp u t pin to inp u t register delay or inp u t pin to logic array delay open-drain o u tp u t sclr/preset oe clko u t ce_o u t aclr/prn clkin ce_in o u tp u t pin delay p r og r ammable p u ll-up re s i s to r b us hold pr n clr n dq o u tp u t register pr n clr n dq pr n clr n dq v ccio data_in0 data_in1 e n a e n a e n a
2?44 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o structure & features programmable delays can increase the register-to-pin delays for output registers. table 2?13 shows the programmable delays for cyclone ii devices. there are two paths in the ioe for an input to reach the logic array. each of the two paths can have a different delay. this allows you to adjust delays from the pin to internal le re gisters that reside in two different areas of the device. you set the two combinational input delays by selecting different delays for two different paths under the input delay from pin to internal cells logic option in the quartus ii software. however, if the pin uses the input register, one of delays is disregarded because the ioe only has two paths to in ternal logic. if the input register is used, the ioe uses one input path. the other input path is then available for the combinational path, and only one input delay assignment is applied. the ioe registers in each i/o block share the same source for clear or preset. you can program preset or clear for each individual ioe, but both features cannot be used simultaneously. you can also program the registers to power up high or low after configuration is complete. if programmed to power up low, an asynchronous clear can control the registers. if programmed to power up high, an asynchronous preset can control the registers. this feature pr events the inadvertent activation of another device?s active-low input upon power up. if one register in an ioe uses a preset or clear signal then all registers in the ioe must use that same signal if they require preset or clear. additionally a synchronous reset signal is availabl e for the ioe registers. external memory interfacing cyclone ii devices support a broad rang e of external memory interfaces such as sdr sdram, ddr sdram, ddr2 sdram, and qdrii sram external memories. cyclone ii devices feature dedicated high-speed interfaces that transfer data between external memory devices at up to 167 mhz/333 mbps for ddr and ddr2 sdram devices and 167 mhz/667 mbps for qdrii sram devices. the programmable dqs delay chain allows you to fi ne tune the phase shift for the input clocks or strobes to properly align clock edges as needed to capture data. table 2?13. cyclone ii progr ammable delay chain programmable delays quartus ii logic option input pin to logic array delay input delay from pin to internal cells input pin to input register delay input delay from pin to input register output pin delay delay from output register to output pin
altera corporation 2?45 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture in cyclone ii devices, all the i/o banks support sdr and ddr sdram memory up to 167 mhz/333 mbps. all i/o banks support dqs signals with the dq bus modes of 8/9, or 16/18. table 2?14 shows the external memory interfaces su pported in cyclone ii devices. cyclone ii devices use data (dq), data strobe (dqs), and clock pins to interface with ex ternal memory. figure 2?26 shows the dq and dqs pins in the 8/9 mode. table 2?14. external memory support in cyclone ii devices note (1) memory standard i/o standard maximum bus width maximum clock rate supported (mhz) maximum data rate supported (mbps) sdr sdram lvttl (2) 72 167 167 ddr sdram sstl-2 class i (2) 72 167 333 (1) sstl-2 class ii (2) 72 133 267 (1) ddr2 sdram sstl-18 class i (2) 72 167 333 (1) sstl-18 class ii (3) 72 125 250 (1) qdrii sram (4) 1.8-v hstl class i (2) 36 167 668 (1) 1.8-v hstl class ii (3) 36 100 400 (1) notes to table 2?14 : (1) the data rate is for designs using the clock delay control circuitry. (2) the i/o standards are supported on al l the i/o banks of the cyclone ii device. (3) the i/o standards are supported only on the i/o ba nks on the top and bottom of the cyclone ii device. (4) for maximum performance, altera recommends using the 1.8-v hstl i/o standard be cause of higher i/o drive strength. qdrii sram devices also su pport the 1.5-v hstl i/o standard.
2?46 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o structure & features figure 2?26. cyclone ii device dq & dqs groups in 8/9 mode notes (1) , (2) notes to figure 2?26 : (1) each dq group consists of a dqs pin, dm pin, and up to nine dq pins. (2) this is an idealized pin layout. for actual pin layout, refer to the pin table. cyclone ii devices support the data strobe or read clock signal (dqs) used in ddr and ddr2 sdram. cy clone ii devices can use either bidirectional data strobes or unidirectional read clocks. the dedicated external memory interface in cyclone ii devices also includes programmable delay circuitry that ca n shift the incoming dqs signals to center align the dqs signals within the data window. the dqs signal is usually associated with a group of data (dq) pins. the phase-shifted dqs signals drive the gl obal clock network, which is used to clock the dq signals on internal le registers. table 2?15 shows the number of dq pin groups per device. dq pins dqs pin dm pin dq pins (2) table 2?15. cyclone ii dqs & dq bus mode support (part 1 of 2) note (1) device package number of 8 groups number of 9 groups (5) , (6) number of 16 groups number of 18 groups (5) , (6) ep2c5 144-pin tqfp (2) 3 300 208-pin pqfp 7 (3) 433 ep2c8 144-pin tqfp (2) 3 300 208-pin pqfp 7 (3) 433 256-pin fineline bga ? 8 (3) 444 ep2c15 256-pin fineline bga 8 4 4 4 484-pin fineline bga 16 (4) 888 ep2c20 256-pin fineline bga 8 4 4 4 484-pin fineline bga 16 (4) 888
altera corporation 2?47 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture you can use any of the dq pins for th e parity pins in cyclone ii devices. the cyclone ii device family supports parity in the 8/9, and 16/18 mode. there is one parity bit available per eight bits of data pins. the data mask, dm, pins are requir ed when writing to ddr sdram and ddr2 sdram devices. a low signal on the dm pin indicates that the write is valid. if the dm signal is high, the memory masks the dq signals. in cyclone ii devices, the dm pins are assigned and are the preferred pins. each group of dqs and dq signals requires a dm pin. when using the cyclone ii i/o banks to interface with the ddr memory, at least one pll with tw o clock outputs is needed to generate the system and write clock. the system clock is used to clock the dq s write signals, commands, and addresses. the write clock is shifted by ?90 from the system clock and is used to cloc k the dq signals during writes. figure 2?27 illustrates ddr sdram interfacing from the i/o through the dedicated circuitry to the logic array. ep2c35 484-pin fineline bga 16 (4) 888 672-pin fineline bga 20 (4) 888 ep2c50 484-pin fineline bga 16 (4) 888 672-pin fineline bga 20 (4) 888 ep2c70 672-pin fineline bga 20 (4) 888 896-pin fineline bga 20 (4) 888 notes to table 2?15 : (1) numbers are preliminary. (2) ep2c5 and ep2c8 devices in the 144-pin tqfp package do not have any dq pin groups in i/o bank 1. (3) because of available clock resources, only a total of 6 dq/dqs grou ps can be implemented. (4) because of available clock resources, only a total of 14 dq/dqs groups can be implemented. (5) the 9 dqs/dq groups are also used as 8 dqs/dq groups. the 18 dqs/dq groups are also used as 16 dqs/dq groups. (6) for qdri implementation, if you connect the d ports (wri te data) to the cyclone ii dq pins, the total available 9 dqs /dq and 18 dqs/dq groups are half of that shown in table 2?15 . table 2?15. cyclone ii dqs & dq bus mode support (part 2 of 2) note (1) device package number of 8 groups number of 9 groups (5) , (6) number of 16 groups number of 18 groups (5) , (6)
2?48 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o structure & features figure 2?27. ddr sdram interfacing f for more information on cyclone ii ex ternal memory interfaces, see the external memo ry interfaces chapter in volume 1 of the cyclone ii device handbook . dqs oe v cc pll gnd clk dq oe dataa datab resynchronizing to system clock global clock clock delay control circuitry -90? shifted clk adjacent lab les clock control block le register le register le register le register t en/dis dynamic enable/disable circuitry enout ena_register_mode le register le register le register le register le register le register le register le register le register
altera corporation 2?49 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture programmable drive strength the output buffer for each cyclone ii device i/o pin has a programmable drive strength control for certain i/o standards. the lvttl, lvcmos, sstl-2 class i and ii, ss tl-18 class i and ii, hstl -18 class i and ii, and hstl-1.5 class i and ii standards have several levels of drive strength that you can control. using minimum settings provides signal slew rate control to reduce system no ise and signal overshoot. table 2?16 shows the possible settings for the i/o stan dards with drive strength control. table 2?16. programmable drive strength (part 1 of 2) note (1) i/o standard i oh /i ol current strength setting (ma) top & bottom i/o pins side i/o pins lvttl (3.3 v) 4 4 88 12 12 16 16 20 20 24 24 lvcmos (3.3 v) 4 4 88 12 12 16 20 24 lvttl/lvcmos (2.5 v) 4 4 88 12 16 lvttl/lvcmos (1.8 v) 2 2 44 66 88 10 10 12 12
2?50 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o structure & features open-drain output cyclone ii devices provide an option al open-drain (equivalent to an open-collector) output for each i/o pi n. this open-drain output enables the device to provide system-level co ntrol signals (that is, interrupt and write-enable signals) that can be asserted by any of several devices. lvcmos (1.5 v) 2 2 44 66 8 sstl-2 class i 8 8 12 12 sstl-2 class ii 16 16 20 24 sstl-18 class i 6 6 88 10 10 12 sstl-18 class ii 16 18 hstl-18 class i 8 8 10 10 12 12 hstl-18 class ii 16 18 20 hstl-15 class i 8 8 10 12 hstl-15 class ii 16 note to table 2?16 : (1) the default current in the quartus ii software is the maximum setting for each i/o standard. table 2?16. programmable drive strength (part 2 of 2) note (1) i/o standard i oh /i ol current strength setting (ma) top & bottom i/o pins side i/o pins
altera corporation 2?51 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture slew rate control slew rate control is performed by using programmable output drive strength. bus hold each cyclone ii device user i/o pi n provides an optional bus-hold feature. the bus-hold circuitry can hold the signal on an i/o pin at its last-driven state. since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not necessary to hold a signal level when the bus is tri-stated. the bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. you can select this featur e individually for each i/o pin. the bus-hold output drives no higher than v ccio to prevent overdriving signals. 1 if the bus-hold feature is enable d, the device cannot use the programmable pull-up option. di sable the bus-hold feature when the i/o pin is configured for differential signals. bus hold circuitry is not available on the dedicated clock pins. the bus-hold circuitry is only active after configuration. when going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. the bus-hold circuitry uses a resistor with a nominal resistance (r bh ) of approximately 7 k to pull the signal level to the last-driven state. refer to the dc characteristics & timing specifications chapter in volume 1 of the cyclone ii devi ce handbook for the specific sustaining current for each v ccio voltage level driven through the resistor and overdrive current used to identify the next driven input level. programmable pull-up resistor each cyclone ii device i/o pin pr ovides an optional programmable pull-up resistor during user mode. if you enable this feature for an i/o pin, the pull-up resistor (typically 25 k ) holds the output to the v ccio level of the output pin?s bank. 1 if the programmable pull-up is enabled, the device cannot use the bus-hold feature. the prog rammable pull-up resistors are not supported on the dedicated configuration, jtag, and dedicated clock pins.
2?52 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o structure & features advanced i/o standard support table 2?17 shows the i/o standards supported by cyclone ii devices and which i/o pins support them. table 2?17. cyclone ii supported i/o standar ds & constraints (part 1 of 2) i/o standard type v ccio level top & bottom i/o pins side i/o pins input output clk, dqs user i/o pins clk, dqs pll_out user i/o pins 3.3-v lvttl and lvcmos (1) single ended 3.3 v/ 2.5 v 3.3 v vvv v v 2.5-v lvttl and lvcmos single ended 3.3 v/ 2.5 v 2.5 v vvv v v 1.8-v lvttl and lvcmos single ended 1.8 v/ 1.5 v 1.8 v vvv v v 1.5-v lvcmos single ended 1.8 v/ 1.5 v 1.5 v vvv v v sstl-2 class i voltage referenced 2.5 v 2.5 v vvv v v sstl-2 class ii voltage referenced 2.5 v 2.5 v vvv v v sstl-18 class i voltage referenced 1.8 v 1.8 v vvv v v sstl-18 class ii voltage referenced 1.8 v 1.8 v vv (2) (2) (2) hstl-18 class i voltage referenced 1.8 v 1.8 v vvv v v hstl-18 class ii voltage referenced 1.8 v 1.8 v vv (2) (2) (2) hstl-15 class i voltage referenced 1.5 v 1.5 v vvv v v hstl-15 class ii voltage referenced 1.5 v 1.5 v vv (2) (2) (2) pci and pci-x (1) (3) single ended 3.3 v 3.3 v vv v differential sstl-2 class i or class ii pseudo differential (4) (5) 2.5 v v 2.5 v (5) v (6) v (6) differential sstl-18 class i or class ii pseudo differential (4) (5) 1.8 v v (7) 1.8 v (5) v (6) v (6)
altera corporation 2?53 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture f for more information on cyclone ii supported i/o standards, see the selectable i/o standards in cyclone ii devices chapter in volume 1 of the cyclone ii devi ce handbook . high-speed differe ntial interfaces cyclone ii devices can transmit and receive data through lvds signals at a data rate of up to 640 mbps and 805 mbps, respectively. for the lvds transmitter and receiver, the cyclone i i device?s input and output pins support serialization and deserial ization through internal logic. differential hstl-15 class i or class ii pseudo differential (4) (5) 1.5 v v (7) 1.5 v (5) v (6) v (6) differential hstl-18 class i or class ii pseudo differential (4) (5) 1.8 v v (7) 1.8 v (5) v (6) v (6) lvds differential 2.5 v 2.5 v vvv v v rsds and mini-lvds ( 8 ) differential (5) 2.5 v vvv lvpecl (9) differential 3.3 v/ 2.5 v/ 1.8 v/ 1.5 v (5) vv notes to table 2?17 : (1) to drive inputs higher than v ccio but less than 4.0 v, disable the pci clamping diode and turn on the allow lvttl and lvcmos input levels to overdrive input buffer option in the quartus ii software. (2) these pins support sstl-18 class ii an d 1.8- and 1.5-v hstl class ii inputs. (3) pci-x does not meet the iv curve requirement at the linear region. pci-clamp diode is not available on top and bottom i/o pins. (4) pseudo-differential hstl and sstl outputs use two si ngle-ended outputs with the second output programmed as inverted. pseudo-differential hstl and sstl inputs treat differential in puts as two single-ended hstl and sstl inputs and only decode one of them. (5) this i/o standard is not supported on these i/o pins. (6) this i/o standard is only suppo rted on the dedicated clock pins. (7) pll_out does not support differential sstl-18 class ii and differential 1.8 and 1.5-v hstl class ii. (8) mini-lvds and rsds are only supported on output pins. (9) lvpecl is only supported on clock inputs. table 2?17. cyclone ii supported i/o standar ds & constraints (part 2 of 2) i/o standard type v ccio level top & bottom i/o pins side i/o pins input output clk, dqs user i/o pins clk, dqs pll_out user i/o pins
2?54 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o structure & features the reduced swing differential signaling (rsds) and mini-lvds standards are derivatives of the lvds standard. the rsds and mini-lvds i/o standards are similar in electrical characteristics to lvds, but have a smaller voltage swing and therefore provide increased power benefits and reduced electr omagnetic interference (emi). cyclone ii devices support the rsds and mini-lvds i/o standards at data rates up to 311 mbps at the transmitter. a subset of pins in each i/o bank (on both rows and columns) support the high-speed i/o interface. the dual-purpose lvds pins require an external-resistor network at the transm itter channels in addition to 100- termination resistors on receiver ch annels. these pins do not contain dedicated serialization or deserialization circuitry. therefore, internal logic performs serialization and deserialization functions. cyclone ii pin tables list the pins that support the high-speed i/o interface. the number of lvds channels supported in each device family member is listed in table 2?18 . table 2?18. cyclone ii device lvds channels (part 1 of 2) device pin count number of lvds channels (1) ep2c5 144 31 (35) 208 56 (60) 256 61 (65) ep2c8 144 29 (33) 208 53 (57) 256 75 (79) ep2c15 256 52 (60) 484 128 (136) ep2c20 240 45 (53) 256 52 (60) 484 128 (136) ep2c35 484 131 (139) 672 201 (209) ep2c50 484 119 (127) 672 189 (197)
altera corporation 2?55 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture you can use i/o pins and internal lo gic to implement a high-speed i/o receiver and transmitter in cyclone ii devices. cyclone ii devices do not contain dedicated seriali zation or deserialization circuitry. therefore, shift registers, internal plls, and ioes are used to perform serial-to-parallel conversions on in coming data and parallel-to-serial conversion on outgoing data. the maximum internal clock frequency for a receiver and for a transmitter is 402.5 mhz. the maximum input data rate of 805 mbps and the maximum output data rate of 64 0 mbps is only achieved when ddio registers are used. the lvds standard does not require an input reference voltage, but it does require a 100- termination resistor between the two signals at the input bu ffer. an external resistor network is required on the transmitter side. f for more information on cyclone ii di fferential i/o interfaces, see the high-speed differential int erfaces in cyclone ii devices chapter in volume 1 of the cyclone ii device handbook . series on-chip termination on-chip termination helps to prevent reflections and maintain signal integrity. this also minimizes the need for external resistors in high pin count ball grid array (bga) packag es. cyclone ii devices provide i/o driver on-chip impedance matching and on-chip series termination for single-ended outputs and bidirectional pins. ep2c70 672 160 (168) 896 257 (265) note to table 2?18 : (1) the first number represents the number of bidirectional i/o pins which can be used as inputs or outputs. the number in parenthesis includes dedicated clock input pin pairs which can only be used as inputs. table 2?18. cyclone ii device lvds channels (part 2 of 2) device pin count number of lvds channels (1)
2?56 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o structure & features cyclone ii devices support driver im pedance matching to the impedance of the transmission line, typically 25 or 50 . when used with the output drivers, on-chip termination sets th e output driver impedance to 25 or 50 . cyclone ii devices also support i/o driver series termination (r s = 50 ) for sstl-2 and sstl-18. table 2?19 lists the i/o standards that support impedance matching and series termination. 1 the recommended frequency rang e of operation is pending silicon charac terization. on-chip series termination can be supported on any i/o bank. v ccio and v ref must be compatible for all i/o pins in order to enable on-chip series termination in a given i/o bank. i/o standards that support different r s values can reside in the same i/o bank as long as their v ccio and v ref are not conflicting. 1 when using on-chip series termination, programmable drive strength is not available. impedance matching is implemented us ing the capabilities of the output driver and is subject to a certain degr ee of variation, depending on the process, voltage and temperature. the actual tolerance is pending silicon characterization. table 2?19. i/o standards supporting series termination note (1) i/o standards target r s ( )v ccio (v) 3.3-v lvttl and lvcmos 25 (2) 3.3 2.5-v lvttl and lvcmos 50 (2) 2.5 1.8-v lvttl and lvcmos 50 (2) 1.8 sstl-2 class i 50 (2) 2.5 sstl-18 class i 50 (2) 1.8 notes to ta b l e 2 ? 1 9 : (1) supported conditions are v ccio =v ccio 50 mv. (2) these r s values are nominal values. actual impedance varies across process, voltage, and temperature conditions.
altera corporation 2?57 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture i/o banks the i/o pins on cyclone ii devices are grouped together into i/o banks and each bank has a separate power bus. ep2c5 and ep2c8 devices have four i/o banks (see figure 2?28 ), while ep2c15, ep2c20, ep2c35, ep2c50, and ep2c70 devices have eight i/o banks (see figure 2?29 ). each device i/o pin is associated with one i/o bank. to accommodate voltage-referenced i/o standards, each cyclone ii i/o bank has a vref bus. each bank in ep2c5, ep2c8, ep2c15, ep2c20, ep2c35, and ep2c50 devices supports two vref pins and each bank of ep2c70 supports four vref pins. when using the vref pins , each vref pin must be properly connected to the appropriate voltage leve l. in the event these pins are not used as vref pins, they may be used as regular i/o pins. the top and bottom i/o banks (ban ks 2 and 4 in ep2c5 and ep2c8 devices and banks 3, 4, 7, and 8 in ep2c15, ep2c20, ep2c35, ep2c50, and ep2c70 devices) support all i/o standards listed in table 2?17 , except the pci/pci-x i/o standards. the left an d right side i/o banks (banks 1 and 3 in ep2c5 and ep2c8 devices and banks 1, 2, 5, and 6 in ep2c15, ep2c20, ep2c35, ep2c50, and ep2c70 devices) support i/o standards listed in table 2?17 , except sstl-18 class ii, hstl-1 8 class ii, and hstl-15 class ii i/o standards. see table 2?17 for a complete list of supported i/o standards. the top and bottom i/o banks (ban ks 2 and 4 in ep2c5 and ep2c8 devices and banks 3, 4, 7, and 8 in ep2c15, ep2c20, ep2c35, ep2c50, and ep2c70 devices) support ddr2 memory up to 167 mhz/333 mbps and qdr memory up to 167 mhz/668 mbps. the left and right side i/o banks (1 and 3 of ep2c5 and ep2c8 devi ces and 1, 2, 5, and 6 of ep2c15, ep2c20, ep2c35, ep2c50 , and ep2c70 devices) only support sdr and ddr sdram interfaces. all the i/o banks of the cyclone ii devices support sdr memory up to 167 mhz/167 mbps and ddr memory up to 167 mhz/333 mbps. 1 ddr2 and qdrii interfaces may be implemented in cyclone ii side banks if the use of class i i/o standard is acceptable.
2?58 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o structure & features figure 2?28. ep2c5 & ep2c8 i/o banks notes (1) , (2) notes to figure 2?28 : (1) this is a top view of the silicon die. (2) this is a graphic representation only. refer to the pi n list and the quartus ii software for exact pin locations. (3) the lvpecl i/o standard is only su pported on clock input pins. this i/o standard is not supported on output pins. (4) the differential sstl-18 and sstl-2 i/o standards are only supported on clock inpu t pins and pll output clock pins. (5) the differential 1.8-v and 1.5-v hstl i/o standards are only supported on clock input pins and pll output clock pins. i/o bank 2 i/o bank 3 i/o bank 4 i/o bank 1 all i/o banks support 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos lvds rsds mini-lvds lvpecl (3) sstl-2 class i and ii sstl-18 class i hstl-18 class i hstl-15 class i differential sstl-2 (4) differential sstl-18 (4) differential hstl-18 (5) differential hstl-15 (5) i/o bank 3 also supports the 3.3-v pci & pci- x i/o standards i/o bank 1 also supports the 3.3-v pci & pci-x i/o standards individual power bus i/o bank 2 also supports the sstl-18 class ii, hstl-18 class ii, & hstl-15 class ii i/o standards i/o bank 4 also supports the sstl-18 class ii, hstl-18 class ii, & hstl-15 class ii i/o standards
altera corporation 2?59 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?29. ep2c15, ep2c20, ep2c 35, ep2c50 & ep2c70 i/o banks notes (1) , (2) notes to figure 2?29 : (1) this is a top view of the silicon die. (2) this is a graphic representation only. refer to the pi n list and the quartus ii software for exact pin locations. (3) the lvpecl i/o standard is only su pported on clock input pins. this i/o standard is not supported on output pins. (4) the differential sstl-18 and sstl-2 i/o standards are only supported on clock inpu t pins and pll output clock pins. (5) the differential 1.8-v and 1.5-v hstl i/o standards are only supported on clock input pins and pll output clock pins. each i/o bank has its own vccio pins. a single de vice can support 1.5-v, 1.8-v, 2.5-v, and 3.3-v interfac es; each individual bank can support a different standard with different i/o voltages. each bank also has dual-purpose vref pins to support any one of the voltage-referenced i/o bank 2 regular i/o block bank 8 regular i/o block bank 7 i/o bank 3 i/o bank 4 i/o bank 1 i/o bank 5 i/o bank 6 individual power bus all i/o banks support 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos lvds rsds mini-lvds lvpecl (3) sstl-2 class i and ii sstl-18 class i hstl-18 class i hstl-15 class i differential sstl-2 (4) differential sstl-18 (4) differential hstl-18 (5) differential hstl-15 (5) i/o banks 3 & 4 also support the sstl-18 class ii, hstl-18 class ii, & hstl-15 class ii i/o standards i/o banks 7 & 8 also support the sstl-18 class ii, hstl-18 class ii, & hstl-15 class ii i/o standards i/o banks 5 & 6 also support the 3.3-v pci & pci-x i/o standard s i/o banks 1 & 2 also support the 3.3-v pci & pci-x i/o standards
2?60 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o structure & features standards (e.g., sstl-2) independently. if an i/o bank does not use voltage-referenced standards, the vref pins are available as user i/o pins. each i/o bank can support multiple standards with the same v ccio for input and output pins. for example, when v ccio is 3.3-v, a bank can support lvttl, lvcmos, and 3.3-v pci for inputs and outputs. voltage-referenced standards can be supported in an i/o bank using any number of single-ended or differential standards as long as they use the same v ref and a compatible v ccio value. multivolt i/o interface the cyclone ii architecture supports th e multivolt i/o interface feature, which allows cyclone ii devices in all packages to interface with systems of different supply voltages. cyclone ii devices have one set of v cc pins ( vccint ) that power the internal device logic array and input buffers that use the lvpecl, lvds, hstl, or sstl i/o standards. cyclone ii devices also have four or eight sets of vcc pins ( vccio ) that power the i/o output drivers and input buffers th at use the lvttl, lvcmos, or pci i/o standards. the cyclone ii vccint pins must always be co nnected to a 1.2-v power supply. if the v ccint level is 1.2 v, then input pi ns are 1.5-v, 1.8-v, 2.5-v, and 3.3-v tolerant. the vccio pins can be connected to either a 1.5-v, 1.8-v, 2.5-v, or 3.3-v power supply, depending on the output requirements. the output levels are co mpatible with systems of the same voltage as the power supply (i.e., when vccio pins are connected to a 1.5-v power supply, the output levels are compatible with 1.5-v systems). when vccio pins are connected to a 3.3-v power supply, the output high is 3.3-v and is compatible with 3.3-v systems. table 2?20 summarizes cyclone ii multivolt i/o support. table 2?20. cyclone ii multivolt i/o support (part 1 of 2) note (1) v ccio (v) input signal output signal 1.5 v 1.8 v 2.5 v 3.3 v 1.5 v 1.8 v 2.5 v 3.3 v 1.5 vv v (2) v (2) v 1.8 v (4) v v (2) v (2) v (3) v 2.5 vv v (5) v (5) v
altera corporation 2?61 february 2007 cyclone ii device handbook, volume 1 cyclone ii architecture 3.3 v (4) v v (6) v (6) v (6) v notes to table 2?20 : (1) the pci clamping diode must be disabled to drive an input with voltages higher than v ccio . (2) these input values overdrive the input buffer, so the pin le akage current is slightly high er than the default value. to drive inputs higher than v ccio but less than 4.0 v, disable the pci clamping diode and turn on allow voltage overdrive for lvttl/lvcmos input pins option in device setting option in the quartus ii software. (3) when v ccio = 1.8-v, a cyclone ii device can drive a 1.5-v device with 1.8-v tolerant inputs. (4) when v ccio = 3.3-v and a 2.5-v input signal feeds an input pin or when v ccio = 1.8-v and a 1.5-v input signal feeds an input pin, the v ccio supply current will be slightly larger than expected. the reason for this increase is that the input signal level does not drive to the v ccio rail, which causes the input buff er to not completely shut off. (5) when v ccio = 2.5-v, a cyclone ii device can drive a 1.5-v or 1.8-v device with 2.5-v tolerant inputs. (6) when v ccio = 3.3-v, a cyclone ii device can drive a 1.5-v, 1.8-v, or 2.5-v device with 3.3-v tolerant inputs. table 2?20. cyclone ii multivolt i/o support (part 2 of 2) note (1) v ccio (v) input signal output signal 1.5 v 1.8 v 2.5 v 3.3 v 1.5 v 1.8 v 2.5 v 3.3 v
2?62 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history document revision history table 2?21 shows the revision history for this document. table 2?21. document revision history date & document version changes made summary of changes february 2007 v3.1 added document revision history. removed table 2-1. updated figure 2?25 . added new note (1) to ta b l e 2 ? 1 7 . added handpara note in ?i/o banks? section. updated note (2) to table 2?20 . removed drive strength control from figure 2?25 . elaboration of ddr2 and qdrii interfaces supported by i/o bank included. november 2005 v2.1 updated table 2?7 . updated figures 2?11 and 2?12 . updated programmable drive strength table. updated table 2?16 . updated table 2?18 . updated table 2?19 . july 2005 v2.0 updated technical content throughout. updated table 2?16 . february 2005 v1.2 updated figure 2-12. november 2004 v1.1 updated table 2?19 . june 2004 v1.0 added document to the cyclone ii device handbook.
altera corporation 3?1 february 2007 3. configuration & testing ieee std. 1149.1 (jtag) boundary scan support all cyclone ? ii devices provide jtag bst circuitry that complies with the ieee std. 1149.1. jtag bounda ry-scan testing can be performed either before or after, but not during configuration. cyclone ii devices can also use the jtag port for co nfiguration with the quartus ? ii software or hardware using either jam files ( .jam ) or jam byte-code files ( .jbc ). cyclone ii devices support ioe i/o standard reconfiguration through the jtag bst chain. the jtag chain ca n update the i/o standard for all input and output pins any time before or during user mode through the config_io instruction. you can use this capability for jtag testing before configuration when some of the cyclone ii pins drive or receive from other devices on the board using voltage-referenced standards. since the cyclone ii device might not be configured before jtag testing, the i/o pins may not be configured for appropriate electrical standards for chip-to-chip communication. pr ogramming the i/o standards via jtag allows you to fully test i /o connections to other devices. f for information on i/o reconfiguration, refer to the morphio: an i/o reconfiguration solution for altera devices white paper . a device operating in jtag mode uses four required pins: tdi , tdo , tms , and tck . the tck pin has an internal weak pull-down resister, while the tdi and tms pins have weak internal pull-up resistors. the tdo output pin and all jtag input pin voltage is determined by the v ccio of the bank where it resides. the bank v ccio selects whether the jtag inputs are 1.5-, 1.8-, 2.5-, or 3.3-v compatible. 1 stratix ? ii, stratix, cyclone ii and cyclone devices must be within the first 8 devi ces in a jtag chain. all of these devices have the same jtag controller. if any of the stratix ii, stratix, cyclone ii or cyclone devices are in the 9th of further position, they fail configuration. this does not affect signal tap ii. cii51003-2.2
3?2 altera corporation cyclone ii device handbook, volume 1 february 2007 ieee std. 1149.1 (jtag) boundary scan support cyclone ii devices also use the jtag port to monitor the logic operation of the device wi th the signaltap ? ii embedded logic analyzer. cyclone ii devices support the jtag instructions shown in table 3?1 . table 3?1. cyclone ii jtag in structions (part 1 of 2) jtag instruction instruction code description sample/preload 00 0000 0101 allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. also used by the signaltap ii embedded logic analyzer. extest (1) 00 0000 1111 allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass 11 1111 1111 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation. usercode 00 0000 0111 selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . idcode 00 0000 0110 selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . highz (1) 00 0000 1011 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices duri ng normal device operation, while tri-stating all of the i/o pins. clamp (1) 00 0000 1010 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices duri ng normal device operation while holding i/o pins to a state defi ned by the data in the boundary-scan register. icr instructions used when configuring a cyclone ii device via the jtag port with a usb blaster ? , byteblaster ? ii, masterblaster ? or byteblastermv ? download cable, or when using a jam file or jbc file via an embedded processor. pulse_nconfig 00 0000 0001 emulates pulsing the nconfig pin low to trigger reconfiguration even though the physical pin is unaffected.
altera corporation 3?3 february 2007 cyclone ii device handbook, volume 1 configuration & testing the quartus ii software has an auto usercode feature where you can choose to use the checksum value of a programming file as the jtag user code. if selected, the checksum is automatically loaded to the usercode register. in the settings dialog box in the assignments menu, click device & pin options , then general, and then turn on the auto usercode option . config_io 00 0000 1101 allows configuration of i/o st andards through the jtag chain for jtag testing. can be executed before, after, or during configuration. stops configuration if executed during configuration. once issued, the config_io instruction holds nstatus low to reset the configuration device. nstatus is held low until the device is reconfigured. signaltap ii instructions monitors internal device operat ion with the signaltap ii embedded logic analyzer. note to ta b l e 3 ? 1 : (1) bus hold and weak pull-up resistor feat ures override the high-impedance state of highz , clamp , and extest. table 3?1. cyclone ii jtag in structions (part 2 of 2) jtag instruction instruction code description
3?4 altera corporation cyclone ii device handbook, volume 1 february 2007 ieee std. 1149.1 (jtag) boundary scan support the cyclone ii device instruction register length is 10 bits and the usercode register length is 32 bits. tables 3?2 and 3?3 show the boundary-scan register length and device idcode information for cyclone ii devices. for more information on the cyclone i i jtag specifications, refer to the dc characteristics & timing specifications chapter in the cyclone ii device handbook, volume 1 . table 3?2. cyclone ii boundary-scan register length device boundary-scan register length ep2c5 498 ep2c8 597 ep2c15 969 ep2c20 969 ep2c35 1,449 ep2c50 1,374 ep2c70 1,890 table 3?3. 32-bit cyclone ii device idcode device idcode (32 bits) (1) version (4 bits) part number (16 bits) man ufacturer identity (11 bits) lsb (1 bit) (2) ep2c5 0000 0010 0000 1011 0001 000 0110 1110 1 ep2c8 0000 0010 0000 1011 0010 000 0110 1110 1 ep2c15 0000 0010 0000 1011 0011 000 0110 1110 1 ep2c20 0000 0010 0000 1011 0011 000 0110 1110 1 ep2c35 0000 0010 0000 1011 0100 000 0110 1110 1 ep2c50 0000 0010 0000 1011 0101 000 0110 1110 1 ep2c70 0000 0010 0000 1011 0110 000 0110 1110 1 notes to ta b l e 3 ? 3 : (1) the most significant bit (msb) is on the left. (2) the idcode?s least significant bit (lsb) is always 1.
altera corporation 3?5 february 2007 cyclone ii device handbook, volume 1 configuration & testing signaltap ii embedded logic analyzer cyclone ii devices support the signaltap ii embedded logic analyzer, which monitors design operation over a period of time through the ieee std. 1149.1 (jtag) circuitry. you ca n analyze internal logic at speed without bringing intern al signals to the i/o pi ns. this feature is particularly important for advanced packages, such as fineline bga ? packages, because it can be difficul t to add a connection to a pin during the debugging process after a board is designed and manufactured. f for more information on the signaltap ii, see the signal tap chapter of the quartus ii handbook, volume 3 . configuration the logic, circuitry, and interconnects in the cyclone ii architecture are configured with cmos sram elem ents. altera fp ga devices are reconfigurable and every device is tested with a high coverage production test program so you do not have to perform fault testing and can instead focus on simulation and design verification. cyclone ii devices are configured at sy stem power-up with data stored in an altera configuration device or provided by a system controller. the cyclone ii device?s optimized interf ace allows the device to act as controller in an active serial conf iguration scheme with epcs serial configuration devices. the serial configuration device can be programmed via srunner, the bytebl aster ii or usb blaster download cable, the altera programming unit (apu), or third-party programmers. in addition to epcs serial configuration devices, altera offers in-system programmability (isp)-capable configur ation devices that can configure cyclone ii devices via a serial data st ream using the passive serial (ps) configuration mode. the ps interfac e also enables microprocessors to treat cyclone ii devices as memory and configure them by writing to a virtual memory location, simplifying reconfiguration. after a cyclone ii device has been configured, it can be reconfigured in-circuit by resetting the device and loading new configurat ion data. real-time changes can be made during system operation, enabling innovative reconfigurable applications. operating modes the cyclone ii architecture uses sram configuration elements that require configuration data to be loaded each time the circuit powers up. the process of physically loading the sram data into the device is called configuration. during initialization, which occurs immediately after configuration, the device resets regist ers, enables i/o pins, and begins to operate as a logic device. you can use the 10mhz internal oscillator or the optional clkusr pin during the initialization. the 10 mhz internal oscillator is disabled in user mode. together, the configuration and initialization processes are called command mode. normal device operation is called user mode.
3?6 altera corporation cyclone ii device handbook, volume 1 february 2007 configuration schemes sram configuration elements allow cyclone ii devices to be reconfigured in-circuit by loading new configuration data into the device. with real-time reconfiguration, the device is forced into command mode with the nconfig pin. the configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. you can perform in-fiel d upgrades by distributing new configuration files within the system or remotely. a built-in weak pull-up resistor pulls all user i/o pins to v ccio before and during device configuration. the configuration pins support 1.5-v/1.8-v or 2.5-v/3.3-v i/o standards. the voltage level of the configuration output pins is determined by the v ccio of the bank where the pins reside. the bank v ccio selects whether the configuration in puts are 1.5-v, 1.8-v, 2.5-v, or 3.3-v compatible. configuration schemes you can load the configuration data for a cyclone ii device with one of three configuration schemes (see table 3?4 ), chosen on the basis of the target application. you can use a configuration device, intelligent controller, or the jtag port to configure a cyclone ii device. a low-cost configuration device can automatically configure a cyclone ii device at system power-up. multiple cyclone ii devices can be configured in any of the three configuration schemes by connect ing the configuration enable ( nce ) and configuration enable output ( nceo ) pins on each device. f for more information on configuration, see the configuring cyclone ii devices chapter of the cyclone ii handbook, volume 2 . table 3?4. data sources for configuration configuration scheme data source active serial (as) low-cost serial configuration device passive serial (ps) enhanced or epc2 c onfiguration device, masterblaster, byteblastermv, byteblaster ii or usb blaster download cable, or serial data source jtag masterblaster, byteblastermv, bytebl aster ii or usb blaster download cable or a microprocessor with a jam or jbc file
altera corporation 3?7 february 2007 cyclone ii device handbook, volume 1 configuration & testing cyclone ii automated single event upset detection cyclone ii devices offer on-chip circ uitry for automated checking of single event upset (seu) detection. some applications that require the device to operate error free at high elevations or in close proximity to earth?s north or south pole require periodic checks to ensure continued data integrity. the error detection cyclic redundancy code (crc) feature controlled by the device & pin options dialog box in the quartus ii software uses a 32-bit crc circuit to en sure data reliability and is one of the best options for mitigating seu. you can implement the error detection crc feature with ex isting circuitry in cyclone ii devices, eliminating the need for external logic. for cyclone ii devices, the crc is pre-computed by quartus ii software and then sent to the device as part of the pof file header. the crc_error pin reports a soft error when configuration sram data is corrupted, indicating to the user to pref orm a device reconfiguration. custom-built circuitry dedicated circuitry in the cyclone i i devices performs error detection automatically. this error detection circuitry in cyclone ii devices constantly checks for errors in the configuration sram cells while the device is in user mode. you can monitor one external pin for the error and use it to trigger a re-configuration cy cle. you can select the desired time between checks by adjusting a built-in clock divider. software interface in the quartus ii software version 4.1 and later, you can turn on the automated error detection crc feature in the device & pin options dialog box. this dialog box allows you to enable the feature and set the internal frequency of the crc checker between 400 khz to 80 mhz. this controls the rate that the crc circuitr y verifies the internal configuration sram bits in the fpga device. f for more information on crc, refer to an: 357 error detection using crc in altera fpgas .
3?8 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history document revision history table 3?5 shows the revision history for this document. table 3?5. document revision history date & document version changes made summary of changes february 2007 v2.2 added document revision history. added new handpara nore in ?ieee std. 1149.1 (jtag) boundary scan support? section. updated ?cyclone ii automated single event upset detection? section. added information about limitation of cascading multi devices in the same jtag chain. corrected information on crc calculation. july 2005 v2.0 updated technical content. february 2005 v1.2 updated information on jtag chain limitations. november 2004 v1.1 updated table 3?4 . june 2004 v1.0 added document to the cyclone ii device handbook.
altera corporation 4?1 february 2007 4. hot socketing & power-on reset introduction cyclone ? ii devices offer hot socketing (a lso known as hot plug-in, hot insertion, or hot swap) and power se quencing support without the use of any external devices. you can insert or remove a cyclone ii board in a system during system operation wi thout causing undesirable effects to the board or to the running system bus. the hot-socketing feature lessens the board design difficulty when using cyclone ii devices on printed circuit boards (pcbs) that also contain a mixture of 3.3-, 2.5-, 1.8-, and 1. 5-v devices. with the cyclone ii hot-socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board. the cyclone ii hot-socketing feature provides: board or device insertion and removal without external components or board manipulation support for any power-up sequence non-intrusive i/o buffers to system buses during hot insertion this chapter also discusses the po wer-on reset (por) circuitry in cyclone ii devices. the por circuitry keeps the devices in the reset state until the v cc is within operating range. cyclone ii hot-socketing specifications cyclone ii devices offer hot-socketing capability with all three features listed above without any external components or special design requirements. the hot-socketing featur e in cyclone ii devices offers the following: the device can be driven before power-up without any damage to the device itself. i/o pins remain tri-stated during power-up. the device does not drive out before or during power- up, thereby affecting other buses in operation. cii51004-3.1
4?2 altera corporation cyclone ii device handbook, volume 1 february 2007 cyclone ii hot-socketing specifications devices can be driv en before power-up you can drive signals into the i/o pins, dedicated input pins, and dedicated clock pins of cyclone ii devi ces before or during power-up or power-down without damaging the device. cyclone ii devices support any power-up or power-down sequence (v ccio and v ccint ) to simplify system level design. i/o pins remain tri-stated during power-up a device that does not support ho t socketing may interrupt system operation or cause contention by driv ing out before or during power-up. in a hot-socketing situation, the cyclone ii device?s output buffers are turned off during system power- up or power-down. the cyclone ii device also does not drive out until the device is configured and has attained proper operating conditions. the i/o pins are tr i-stated until the device enters user mode with a weak pull-up resistor (r) to 3.3v. refer to figure 4?1 for more information. 1 you can power up or power down the v ccio and v ccint pins in any sequence. the v ccio and v ccint must have monotonic rise to their steady state levels. (refer to figure 4?3 for more information.) the power supply ramp rates can range from 100 s to 100 ms for non ?a? devices. both v cc supplies must power down within 100 ms of ea ch other to prevent i/o pins from driving out. during hot socketing, the i/o pin capacitance is less than 15 pf and the clock pi n capacitance is less than 20 pf. cyclone ii devices meet th e following hot-socketing specification. the hot-socketing dc specification is | i iopin | < 300 a. the hot-socketing ac specification is | i iopin | < 8 ma for 10 ns or less. this specification takes into account the pin capacitance but not board trace and external loading capacitanc e. you must cons ider additional capacitance for trace, connector, and loading separately. i iopin is the current at any user i/o pin on the device. the dc specification applies when all v cc supplies to the device are stable in the powered-up or powered-down conditio ns. for the ac specification, the peak current duration due to power- up transients is 10 ns or less. a possible concern for semiconducto r devices in general regarding hot socketing is the potential for latch-up . latch-up can occur when electrical subsystems are hot socketed into an ac tive system. during hot socketing, the signal pins may be connected and driven by the active system before
altera corporation 4?3 february 2007 cyclone ii device handbook, volume 1 hot socketing & power-on reset the power supply can provide current to the device?s v cc and ground planes. this condition can lead to latch-up and cause a low-impedance path from v cc to ground within the device. as a result, the device extends a large amount of current, possibly causing electrical damage. altera has ensured by design of the i/o buffers and hot-socketing circuitry, that cyclone ii devices are immune to latch-up during hot socketing. hot-socketing feature implementation in cyclone ii devices the hot-socketing feature turns off th e output buffer during power up (either v ccint or v ccio supplies) or power down. the hot-socket circuit generates an internal hotsckt signal when either v ccint or v ccio is below the threshold voltag e. designs cannot use the hotsckt signal for other purposes. the hotsckt signal cuts off the output buffer to ensure that no dc current (except for we ak pull-up leakag e current) leaks through the pin. when v cc ramps up slowly, v cc is still relatively low even after the internal por signal (not available to the fpga fabric used by customer designs) is released and the configuration is finished. the conf_done , nceo , and nstatus pins fail to respon d, as the output buffer cannot drive out because the ho t-socketing circuitry keeps the i/o pins tristated at this low v cc voltage. therefore, the hot-socketing circuit has been removed on these configurat ion output or bidirectional pins to ensure that they are able to operate during configuration. these pins are expected to drive out during power-up and power-down sequences. each i/o pin has the circuitry shown in figure 4?1 .
4?4 altera corporation cyclone ii device handbook, volume 1 february 2007 hot-socketing feature implementation in cyclone ii devices figure 4?1. hot-socketing circuit bloc k diagram for cyclone ii devices the por circuit monitors v ccint voltage level and keeps i/o pins tri-stated until the device is in user mode. the weak pull-up resistor (r) from the i/o pin to v ccio keeps the i/o pins from floating. the voltage tolerance control circuit permits the i/o pins to be driven by 3.3 v before v ccio and/or v ccint are powered, and it prevents the i/o pins from driving out when the device is not in user mode. f for more information, see the dc characteristics & timing specifications chapter in volume 1 of the cyclone ii device handbook for the value of the internal weak pull-up resistors. figure 4?2 shows a transistor level cross section of the cyclone ii device i/o buffers. this design ensures th at the output buffers do not drive when v ccio is powered before v ccint or if the i/o pad voltage is higher than v ccio . this also applies for sudden voltage spikes during hot socketing. the v pad leakage current charges th e voltage tolerance control circuit capacitance. output enable output hot socket output pre-driver voltage tolerance control power-on reset monitor weak pull-up resistor pad input buffer to logic array r
altera corporation 4?5 february 2007 cyclone ii device handbook, volume 1 hot socketing & power-on reset figure 4?2. transistor level diagram of fpga device i/o buffers notes to figure 4?2 : (1) this is the logic array signal or the larger of either the v ccio or v pa d signal. (2) this is the larger of either the v ccio or v pad signal. power-on reset circuitry cyclone ii devices contain por circuitry to keep the device in a reset state until the power supply voltage levels have stabilized during power-up. the por circuit monitors the v ccint voltage levels and tri-states all user i/o pins until the v cc reaches the recommended operating levels. in addition, the por circuitry also monitors the v ccio level of the two i/o banks that contains configuration pi ns (i/o banks 1 and 3 for ep2c5 and ep2c8, i/o banks 2 and 6 for ep2c 15a, ep2c20, ep2c35, ep2c50, and ep2c70) and tri-states all user i/o pins until the v cc reaches the recommended operating levels. after the cyclone ii device enters user mode, the por circuit continues to monitor the v ccint voltage level so that a brown-out condition during user mode can be detected. if the v ccint voltage sags below the por trip point during user mode, the por circuit resets the device. if the v ccio voltage sags during user mode, the po r circuit does not reset the device. "wake-up" time for cyclone ii devices in some applications, it may be nece ssary for a device to wake up very quickly in order to begin operation. the cyclone ii device family offers the fast-on feature to support fast wake-up time applications. devices that support the fast-on feature ar e designated with an ?a? in the ordering code and have stricter po wer up requirements compared to non- a devices. logic array signal (1) (2) v ccio v pad n+ n+ n-well n+ p+ p+ p-well p-substrate
4?6 altera corporation cyclone ii device handbook, volume 1 february 2007 power-on reset circuitry for cyclone ii devices, wake-up time consists of power-up, por, configuration, and initialization. the device must properly go through all four stages to configure correctly and begin operation. you can calculate wake-up time using the following equation: figure 4?3 illustrates the componen ts of wake up time. figure 4?3. cyclone ii wake-up time note to figure 4?3 : (1) v cc ramp must be monotonic. the v cc ramp time and por time wi ll depend on the device characteristics and the power supply used in your system. the fast-on devices require a maximum v cc ramp time of 2 ms and have a maximum por time of 12 ms. configuration time will depend on the configuration mode chosen and the configuration file size. you ca n calculate configuration time by multiplying the number of bits in the configuration file with the period of the configuration clock. for fast configuration times, you should use passive serial (ps) configuration mode with maximum dclk frequency of 100 mhz. in addition, you ca n use compression to reduce the configuration file size and speed up the configuration time. the t cd2um or t cd2umc parameters will determine the initialization time. 1 for more information on the t cd2um or t cd2umc parameters, refer to the configuring cyclone ii devices chapter in the cyclone ii device handbook . wake-up time = v cc ramp time + por time + configuration time + initialization tim e v cc ramp time por time configuration time initialization time v cc minimum voltage time user mode
altera corporation 4?7 february 2007 cyclone ii device handbook, volume 1 hot socketing & power-on reset if you cannot meet the maximum v cc ramp time requirement, you must use an external component to hold nconfig low until the power supplies have reached their minimum recommend operating levels. otherwise, the device may not properly co nfigure and enter user mode. conclusion cyclone ii devices are hot socketable and support all power-up and power-down sequences with the one requirement that v ccio and v ccint be powered up and down within 100 ms of each other to keep the i/o pins from driving out. cyclone ii devices do not require any external devices for hot socketing and power sequencing. document revision history table 4?1 shows the revision history for this document. table 4?1. document revision history date & document version changes made summary of changes february 2007 v3.1 added document revision history. updated ?i/o pins remain tri-stated during power-up? section. updated ?power-on reset circuitry? section. added footnote to figure 4?3 . specified v ccio and v ccint supplies must be gnd when "not powered". added clarification about input-tristate behavior. added infomation on v cc monotonic ramp. july 2005 v2.0 updated technical content throughout. february 2005 v1.1 removed esd section. june 2004 v1.0 added document to the cyclone ii device handbook.
4?8 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history
altera corporation 5?1 february 2007 5. dc characteristics & timing specifications operating conditions cyclone ? ii devices are offered in commercial, industrial, and extended temperature grades. commercial devices are offered in -6 (fastest), -7, -8 speed grades. all parameter limits are representati ve of worst-case supply voltage and junction temperature conditions. unle ss otherwise noted, the parameter values in this chapter apply to all cyclone ii devices. ac and dc characteristics are specified using the same numbers for both commercial and industrial grades. al l parameters representing voltages are measured with respect to ground. tables 5?1 through 5?4 provide information on absolute maximum ratings. table 5?1. cyclone ii device absolute maximum ratings notes (1) , (2) symbol parameter conditi ons minimum maximum unit v ccint supply voltage with respect to ground ?0.5 1.8 v v ccio output supply voltage ?0.5 4.6 v v cca _ pll [1..4] pll supply voltage ?0.5 1.8 v v in dc input voltage (3) ?0.5 4.6 v i out dc output current, per pin ?25 40 ma t stg storage temperature no bias ?65 150 c t j junction temperature bga packages under bias 125 c notes to ta b l e 5 ? 1 : (1) conditions beyond those listed in this table cause pe rmanent damage to a device. these are stress ratings only. functional operation at these levels or any other conditions beyond those specified in this chapter is not implied. additionally, device operation at the absolute maximum ra tings for extended periods of time may have adverse affects on the device reliability. (2) see the operating requirements for altera devices data sheet for more information. (3) during transitions, the inputs may over shoot to the voltage shown in table 5?4 based upon the input duty cycle. the dc case is equivalent to 100% duty cycle. during transition, the inputs may undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. cii51005-3.1
5?2 altera corporation cyclone ii device handbook, volume 1 february 2007 operating conditions table 5?2 specifies the recommended operating conditions for cyclone ii devices. it shows the allowed voltage ranges for v ccint , v ccio , and the operating junction temperature (t j ). the lvttl and lvcmos inputs are powered by v ccio only. the lvds and lvpecl input buffers on dedicated clock pins are powered by v ccint . the sstl, hstl, lvds input buffers are powered by both v ccint and v ccio . table 5?2. recommended operating conditions symbol parameter conditions minimum maximum unit v ccint supply voltage for internal logic and input buffers (1) 1.15 1.25 v v ccio (2) supply voltage for output buffers, 3.3-v operation (1) 3.135 (3.00) 3.465 (3.60) (3) v supply voltage for output buffers, 2.5-v operation (1) 2.375 2.625 v supply voltage for output buffers, 1.8-v operation (1) 1.71 1.89 v supply voltage for output buffers, 1.5-v operation (1) 1.425 1.575 v t j operating junction temperature for commercial use 0 85 c for industrial use ?40 100 c for extended temperature use ?40 125 c notes to ta b l e 5 ? 2 : (1) the v cc must rise monotonically. the maximum v cc (both v ccio and v ccint ) rise time is 100 ms for non-a devices and 2 ms for a devices. (2) the v ccio range given here spans the lowest and highest oper ating voltages of all supp orted i/o standards. the recommended v ccio range specific to each of the sing le-ended i/o standards is given in table 5?6 , and those specific to the differential standards is given in table 5?8 . (3) the minimum and maximum values of 3.0 v and 3.6 v, respectively, for v ccio only applies to the pci and pci-x i/o standards. see table 5?6 for the voltage range of other i/o standards.
altera corporation 5?3 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?3. dc characteristics fo r user i/o, dual-purpose, & dedicated pins (part 1 of 2) symbol parameter conditions minimum typical maximum unit v in input voltage (1) , (2) ?0.5 4.0 v i i input pin leakage current v in = v cciomax to 0 v (3) ?10 10 a v out output voltage 0 v ccio v i oz tri-stated i/o pin leakage current v out = v cciomax to 0 v (3) ?10 10 a i ccint0 v ccint supply current (standby) v in = ground, no load, no toggling inputs t j = 25 c nominal v ccint ep2c5 0.010 (4) a ep2c8 0.017 (4) a ep2c15 0.037 (4) a ep2c20 0.037 (4) a ep2c35 0.066 (4) a ep2c50 0.101 (4) a ep2c70 0.141 (4) a i ccio0 v ccio supply current (standby) v in = ground, no load, no toggling inputs t j = 25 c v ccio = 2.5 v ep2c5 0.7 (4) ma ep2c8 0.8 (4) ma ep2c15 0.9 (4) ma ep2c20 0.9 (4) ma ep2c35 1.3 (4) ma ep2c50 1.3 (4) ma ep2c70 1.7 (4) ma
5?4 altera corporation cyclone ii device handbook, volume 1 february 2007 operating conditions table 5?4 shows the maximum v in overshoot voltage and the dependency on the duty cycl e of the input signal. see table 5?3 for more information. r conf (5) value of i/o pin pull-up resistor before and during configuration v in = 0 v, v ccio = 3.3 v +/-10% (6) , (7) 10 25 50 k v in = 0 v, v ccio = 2.5 v +/-5% (6) , (7) 15 35 60 k v in = 0 v, v ccio = 1.8 v +/-5% (6) , (7) 30 65 120 k v in = 0 v, v ccio = 1.5 v +/-5% (6) , (7) 40 85 140 k recommended value of i/o pin external pull- down resistor before and during configuration (7) ( 8 ) 12k notes to ta b l e 5 ? 3 : (1) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v ccint and v ccio are powered. (2) the minimum dc input is ?0.5 v. du ring transitions, the inputs may unde rshoot to ?2.0 v or overshoot to the voltages shown in table 5?4 , based on input duty cycle for input curren ts less than 100 ma. the overshoot is dependent upon duty cycle of the signal. the dc case is eq uivalent to 100% duty cycle. (3) this value is specified for normal device operation. the value may vary during power-up. this applies for all v ccio settings (3.3, 2.5, 1.8, and 1.5 v). (4) maximum values depend on the actual t j and design utilization. see the excel-based powerplay early power estimator ( www.altera.com ) or the quartus ii powerplay power analyzer feature for maximum values. see the section ?power consumption? on page 5?13 for more information. (5) r conf values are based on characterization. r conf = v ccio /i rconf . r conf values may be different if v i value is not 0 v. (6) pin pull-up resistance values may be lower if an external source drives the pin higher than v ccio . (7) minimum condition at -40 c and high v cc , typical condition at 25 c and nominal v cc and maximum condition at 125 c and low v cc for r conf values. (8) these values apply to all v ccio settings. table 5?3. dc characteristics fo r user i/o, dual-purpose, & dedicated pins (part 2 of 2) symbol parameter conditions minimum typical maximum unit table 5?4. v in overshoot voltage fo r all input buffers maximum v in (v) input signal duty cycle 4.0 100% (dc) 4.1 90% 4.2 50% 4.3 30% 4.4 17% 4.5 10%
altera corporation 5?5 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications single-ended i/o standards tables 5?6 and 5?7 provide operating condition information when using single-ended i/o standards with cyclone ii devices. table 5?5 provides descriptions for the voltage and current symbols used in tables 5?6 and 5?7 . table 5?5. voltage & curr ent symbol definitions symbol definition v ccio supply voltage for single-ended inputs and for output drivers v ref reference voltage for setting the input switching threshold v il input voltage that indicates a low logic level v ih input voltage that indicates a high logic level v ol output voltage that indicates a low logic level v oh output voltage that indicates a high logic level i ol output current condition under which v ol is tested i oh output current condition under which v oh is tested v tt voltage applied to a resistor termination as specified by hstl and sstl standards table 5?6. recommended operating conditions for user i/o pins using single-ended i/o standards (part 1 of 2) note (1) i/o standard v ccio (v) v ref (v) v il (v) v ih (v) min typ max min typ max max min 3.3-v lvttl and lvcmos 3.135 3.3 3.465 0.8 1.7 2.5-v lvttl and lvcmos 2.375 2.5 2.625 0.7 1.7 1.8-v lvttl and lvcmos 1.710 1.8 1.890 0.35 v ccio 0.65 v ccio 1.5-v lv c m o s 1.425 1.5 1.575 0.35 v ccio 0.65 v ccio pci and pci-x 3.000 3.3 3.600 0.3 v ccio 0.5 v ccio sstl-2 class i 2.375 2.5 2.625 1.19 1.25 1.31 v ref ? 0.18 (dc) v ref ? 0.35 (ac) v ref + 0.18 (dc) v ref + 0.35 (ac) sstl-2 class ii 2.375 2.5 2.625 1.19 1.25 1.31 v ref ? 0.18 (dc) v ref ? 0.35 (ac) v ref + 0.18 (dc) v ref + 0.35 (ac)
5?6 altera corporation cyclone ii device handbook, volume 1 february 2007 operating conditions sstl-18 class i 1.7 1.8 1.9 0.833 0.9 0.969 v ref ? 0.125 (dc) v ref ? 0.25 (ac) v ref + 0.125 (dc) v ref + 0.25 (ac) sstl-18 class ii 1.7 1.8 1.9 0.833 0.9 0.969 v ref ? 0.125 (dc) v ref ? 0.25 (ac) v ref + 0.125 (dc) v ref + 0.25 (ac) 1.8-v hstl class i 1.71 1.8 1.89 0.85 0.9 0.95 v ref ? 0.1 (dc) v ref ? 0.2 (ac) v ref + 0.1 (dc) v ref + 0.2 (ac) 1.8-v hstl class ii 1.71 1.8 1.89 0.85 0.9 0.95 v ref ? 0.1 (dc) v ref ? 0.2 (ac) v ref + 0.1 (dc) v ref + 0.2 (ac) 1.5-v hstl class i 1.425 1.5 1.575 0.71 0.75 0.79 v ref ? 0.1 (dc) v ref ? 0.2 (ac) v ref + 0.1 (dc) v ref + 0.2 (ac) 1.5-v hstl class ii 1.425 1.5 1.575 0.71 0.75 0.79 v ref ? 0.1 (dc) v ref ? 0.2 (ac) v ref + 0.1 (dc) v ref + 0.2 (ac) note to ta b l e 5 ? 6 : (1) nominal values (nom) are for t a = 25 c, v ccint = 1.2 v, and v ccio = 1.5, 1.8, 2.5, and 3.3 v. table 5?7. dc characteristics of user i/o pi ns using single-ended standards (part 1 of 2) notes (1) , (2) i/o standard test conditions voltage thresholds i ol (ma) i oh (ma) maximum v ol (v) minimum v oh (v) 3.3-v lvttl 4 ?4 0.45 2.4 3.3-v lvcmos 0.1 ?0.1 0.2 v ccio ? 0.2 2.5-v lvttl and lvcmos 1?1 0.4 2.0 1.8-v lvttl and lvcmos 2?2 0.45 v ccio ? 0.45 1.5-v lvttl and lvcmos 2?20.25 v ccio 0.75 v ccio pci and pci-x 1.5 ?0.5 0.1 v ccio 0.9 v ccio sstl-2 class i 8.1 ?8.1 v tt ? 0.57 v tt + 0.57 sstl-2 class ii 16.4 ?16.4 v tt ? 0.76 v tt + 0.76 sstl-18 class i 6.7 ?6.7 v tt ? 0.475 v tt + 0.475 sstl-18 class ii 13.4 ?13.4 0.28 v ccio ? 0.28 1.8-v hstl class i 8 ?8 0.4 v ccio ? 0.4 table 5?6. recommended operating conditions for user i/o pins using single-ended i/o standards (part 2 of 2) note (1) i/o standard v ccio (v) v ref (v) v il (v) v ih (v) min typ max min typ max max min
altera corporation 5?7 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications differential i/o standards the rsds and mini-lvds i/o standard s are only supported on output pins. the lvds i/o standard is suppo rted on both receiver input pins and transmitter output pins. 1 for more information on how th ese differential i/o standards are implemented, see the high-speed differenti al interfaces in cyclone ii devices chapter in volume 1 of the cyclone ii device handbook . figure 5?1 shows the receiver input waveforms for all differential i/o standards (lvds, lvpecl, different ial 1.5-v hstl class i and ii, differential 1.8-v hstl class i and ii, differential sstl-2 class i and ii, and differential sstl-18 class i and ii). 1.8-v hstl class ii 16 ?16 0.4 v ccio ? 0.4 1.5-v hstl class i 8 ?8 0.4 v ccio ? 0.4 1.5v hstl class ii 16 ?16 0.4 v ccio ? 0.4 notes to ta b l e 5 ? 7 : (1) the values in this table are ba sed on the conditions listed in tables 5?2 and 5?6 . (2) this specification is supported across all the programmable drive settings available as shown in the cyclone ii architecture chapter of the cyclone ii device handbook . table 5?7. dc characteristics of user i/o pi ns using single-ended standards (part 2 of 2) notes (1) , (2) i/o standard test conditions voltage thresholds i ol (ma) i oh (ma) maximum v ol (v) minimum v oh (v)
5?8 altera corporation cyclone ii device handbook, volume 1 february 2007 operating conditions figure 5?1. receiver input waveform s for differential i/o standards notes to figure 5?1 : (1) v id is the differential input voltage. v id = |p ? n|. (2) v icm is the input common mode voltage. v icm = (p + n)/2. (3) the p ? n waveform is a function of the positive channel (p) and the negative channel (n). single-ended waveform differential waveform (mathematical function of positive & negative channel) positive channel (p) = v ih negative channel (n) = v il ground v id (1) v id (1) v id (1) v icm (2) 0 v p ? n (3)
altera corporation 5?9 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?8 shows the recommended operating conditions for user i/o pins with differential i/o standards. table 5?8. recommended operating conditions for user i/o pins using differ ential signal i/o standards i/o standard v ccio (v) v id (v) (1) v icm (v) v il (v) v ih (v) min typ max min typ max min typ max min max min max lvds 2.375 2.5 2.625 0.1 0.65 0.1 2.0 mini-lvds (2) 2.375 2.5 2.625 rsds (2) 2.375 2.5 2.625 lvpecl (3) (6) 3.135 3.3 3.465 0.1 0.6 0.95 0 2.2 2.1 2.88 differential 1.5-v hstl class i and ii (4) 1.425 1.5 1.575 0.2 v ccio + 0.6 0.68 0.9 v ref ? 0.20 v ref + 0.20 differential 1.8-v hstl class i and ii (4) 1.71 1.8 1.89 v ref ? 0.20 v ref + 0.20 differential sstl-2 class i and ii (5) 2.375 2.5 2.625 0.36 v ccio + 0.6 0.5 v ccio ? 0.2 0.5 v ccio 0.5 v ccio + 0.2 v ref ? 0.35 v ref + 0.35 differential sstl-18 class i and ii (5) 1.7 1.8 1.9 0.25 v ccio + 0.6 0.5 v ccio ? 0.2 0.5 v ccio 0.5 v ccio + 0.2 v ref ? 0.25 v ref + 0.25 notes to ta b l e 5 ? 8 : (1) refer to the high-speed differential interfaces in cyclone ii devices chapter in volume 1 of the cyclone ii device handbook for measurement conditions on v id . (2) the rsds and mini-lvds i/o standard s are only supported on output pins. (3) the lvpecl i/o standard is only supported on clock in put pins. this i/o standard is not supported on output pins. (4) the differential 1.8-v and 1.5-v hstl i/o standards are only supported on clock input pins and pll output clock pins. (5) the differential sstl-18 and sstl-2 i/o standards are only supported on clock input pins and pll output clock pins. (6) the lvpecl clock inputs are powered by v ccint and support all v ccio settings. however, it is recommended to connect v ccio to typical value of 3.3v.
5?10 altera corporation cyclone ii device handbook, volume 1 february 2007 operating conditions figure 5?2 shows the transmitter output waveforms for all supported differential output standards (lvds, mini-lvds, rsds, differential 1.5-v hstl class i and ii , differential 1.8-v hstl cl ass i and ii, differential sstl-2 class i and ii , and differential ss tl-18 class i and ii). figure 5?2. transmitter output wavefo rms for differential i/o standards notes to figure 5?2 : (1) v od is the output differential voltage. v od = |p ? n|. (2) v ocm is the output common mode voltage. v ocm = (p + n)/2. (3) the p ? n waveform is a function of the positive channel (p) and the negative channel (n). table 5?9 shows the dc characteristics for user i/o pins with differential i/o standards. single-ended waveform differential waveform (mathematical function of positive & negative channel) positive channel (p) = v oh negative channel (n) = v ol ground v od (1) v od (1) v od (1) 0 v v ocm (2) p ? n (3) table 5?9. dc characteristics fo r user i/o pins using differ ential i/o standards (part 1 of 2) note (1) i/o standard v od (mv) v od (mv) v ocm (v) v oh (v) v ol (v) min typ max min max min typ max min max min max lvds 250 600 50 1.125 1.25 1.375 mini-lvds (2) 300 600 50 1.125 1.25 1.375 rsds (2) 100 600 1.125 1.25 1.375 differential 1.5-v hstl class i and ii (3) v ccio ? 0.4 0.4 differential 1.8-v hstl class i and ii (3) v ccio ? 0.4 0.4
altera corporation 5?11 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications dc characteristics for different pin types table 5?10 shows which types of pins that support bus hold circuitry. differential sstl-2 class i (4) v tt + 0.57 v tt ? 0.57 differential sstl-2 class ii (4) v tt + 0.76 v tt ? 0.76 differential sstl-18 class i (4) 0.5 v ccio ? 0.125 0.5 v ccio 0.5 v ccio + 0.125 v tt + 0.475 v tt ? 0.475 differential sstl-18 class ii (4) 0.5 v ccio ? 0.125 0.5 v ccio 0.5 v ccio + 0.125 v ccio ? 0.28 0.28 notes to ta b l e 5 ? 9 : (1) the lvpecl i/o standard is only supported on clock in put pins. this i/o standard is not supported on output pins. (2) the rsds and mini-lvds i/o standard s are only supported on output pins. (3) the differential 1.8-v hstl and differential 1.5-v hstl i/o standards are only supported on clock input pins and pll output clock pins. (4) the differential sstl-18 and sstl-2 i/o standards are only supported on clock input pins and pll output clock pins. table 5?9. dc characteristics fo r user i/o pins using differ ential i/o standards (part 2 of 2) note (1) i/o standard v od (mv) v od (mv) v ocm (v) v oh (v) v ol (v) min typ max min max min typ max min max min max table 5?10. bus hold support pin type bus hold i/o pins using single-ended i/o standards yes i/o pins using differential i/o standards no dedicated clock pins no jtag no configuration pins no
5?12 altera corporation cyclone ii device handbook, volume 1 february 2007 dc characteristics for different pin types table 5?11 specifies the bus hold para meters for general i/o pins. on-chip termination specifications table 5?12 defines the specifications for internal termination resistance tolerance when using series or differential on-chip termination. table 5?11. bus hold parameters note (1) parameter conditions v ccio level unit 1.8 v 2.5 v 3.3 v min max min max min max bus-hold low, sustaining current v in > v il (maximum) 30 50 70 a bus-hold high, sustaining current v in < v il (minimum) ?30 ?50 ?70 a bus-hold low, overdrive current 0 v < v in < v ccio 200 300 500 a bus-hold high, overdrive current 0 v < v in < v ccio ?200 ?300 ?500 a bus-hold trip point (2) 0.68 1.07 0.7 1.7 0.8 2.0 v notes to ta b l e 5 ? 11 : (1) there is no specification for bus-hold at v ccio = 1.5 v for the hstl i/o standard. (2) the bus-hold trip points are based on calc ulated input voltages from the jedec standard. table 5?12. series on-chip te rmination specifications symbol description conditions resistance tolerance commercial max industrial max extended temp max unit 25- r s internal series termination without calibration (25- setting ) v ccio = 3.3v 30 30 40 % 50- r s internal series termination without calibration (50- setting ) v ccio = 2.5v 30 30 40 % 50- r s internal series termination without calibration (50- setting ) v ccio = 1.8v 30 (1) 30 (1) 50 % note to table 5?12 : (1) for commercial, industrial, and extended -8 devices, the tolerance is 40%.
altera corporation 5?13 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?13 shows the cyclone ii device pi n capacitance for different i/o pin types. power consumption you can calculate the power usage for your design using the powerplay early power estimator and the powerplay power analyzer feature in the quartus ? ii software. the interactive powerplay early power estimator is typically used during the early stages of fpga design , prior to finalizing the project, in order to get a magnitude estimate of the device power. the quartus ii software powerplay power analyzer fe ature is typically used during the later stages of fpga design. the po werplay power analyzer also allows you to apply test vectors against yo ur design for more accurate power consumption modeling. in both cases, only use these calculat ions as an estimation of power, not as a specification. for more informat ion on powerplay tools, refer to the powerplay early power estimator user guide and the powerplay early power estimator and powerplay power analyzer chapters in volume 3 of the quartus ii handbook. 1 you can obtain the excel-ba sed powerplay early power estimator at www.altera.com . see table 5?3 on page 5?3 for typical i cc standby specifications. the power-up current required by cy clone ii devices does not exceed the maximum static current. the rate at which the current increases is a function of the system power suppl y. the exact amount of current table 5?13. device capacitance note (1) symbol parameter typical unit c io input capacitance for user i/o pin 6 pf c lvds input capacitance for dual-purpose lvds/user i/o pin 6 pf c vref input capacitance for dual-purpose vref pin when used as vref or user i/o pin 21 pf c clk input capacitance for clock pin. 5 pf note to table 5?13 : (1) capacitance is sample-tested only. ca pacitance is measured using time-domain reflectometry (tdr). measurement accuracy is within 0.5 pf.
5?14 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications consumed varies according to the process, temperature, and power ramp rate. the duration of the i ccint power-up requirement depends on the v ccint voltage supply rise time. you should select power supplies and regulators that can supply the amount of current required when designing with cyclone ii devices. altera recommends using the cy clone ii powerpla y early power estimator to estima te the user-mode i ccint consumption and then select power supplies or regulators based on the values obtained. timing specifications the directdrive? technology and multitrack? interconnect ensure predictable performance, accurate simulation, and ac curate timing analysis across al l cyclone ii device densities and speed grades. this section describes and specifies the performance, internal, external, high-speed i/o, jtag, and pll timing specifications. this section shows the timing models for cyclone ii devices. commercial devices meet this timing over the commercial temperature range. industrial devices meet this timing ov er the industrial temperature range. extended devices meet this timing ov er the extended temperature range. all specifications are representative of worst-case supply voltage and junction temperature conditions. 1 the timing numbers listed in th e tables of this section are extracted from the quartus ? ii software version 6.0. preliminary & final ti ming specifications timing models can have either prelim inary or final status. the quartus ii software issues an informational me ssage during the design compilation if the timing models are preliminary. table 5?14 shows the status of the cyclone ii device timing models. preliminary status means the timing model is subject to change. initially, timing numbers are created using simulation results, process data, and other known parameters. these tests are used to make the preliminary numbers as close to the actual timing parameters as possible.
altera corporation 5?15 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications final timing numbers are based on ac tual device operation and testing. these numbers reflect the actual performance of the device under worst-case voltage and juncti on temperature conditions. performance table 5?15 shows cyclone ii performance for some common designs. all performance values were obtained with quartus ii software compilation of lpm, or megacore functions for the fir and fft designs. table 5?14. cyclone ii device timing model status device preliminary final ep2c5 v ep2c8 v ep2c15 v ep2c20 v ep2c35 v ep2c50 v ep2c70 v table 5?15. cyclone ii performance (part 1 of 4) note (1) applications resources used performance les m4k memory blocks dsp blocks -6 speed grade -7 speed grade -8 speed grade units le 16-to-1 multiplexer (2) 21 0 0 385.35 313.97 286.04 mhz 32-to-1 multiplexer (2) 38 0 0 294.2 260.75 191.02 mhz 16-bit counter 16 0 0 401.6 349.4 310.65 mhz 64-bit counter 64 0 0 157.15 137.98 126.27 mhz
5?16 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications memory m4k block simple dual-port ram 128x36 bit (4) , (6) 0 1 0 235.29 194.93 163.13 mhz true dual-port ram 128x18 bit (4) , (6) 0 1 0 235.29 194.93 163.13 mhz fifo 128x16 bit (6) 32 1 0 235.29 194.93 163.13 mhz simple dual-port ram 128x36 bit (5) , (6) 0 1 0 210.08 195.0 163.02 mhz true dual-port ram 128x18 bit (5) , (6) 0 1 0 163.02 163.02 163.02 mhz dsp block 9x9-bit multiplier (3) 0 0 1 260.01 216.73 180.57 mhz 18x18-bit multiplier (3) 0 0 1 260.01 216.73 180.57 mhz 18-bit, 4 tap fir filter 113 0 8 182.74 147.47 122.98 mhz larger designs 8-bit, 16 tap parallel fir filter 52 0 4 153.56 131.25 110.57 mhz 8-bit, 1024pt, streaming, 3mults/5 adders fft function 3191 22 9 235.07 195.0 163.02 mhz 8-bit, 1024pt, streaming, 4mults/2 adders fft function 3041 22 12 235.07 195.0 163.02 mhz 8-bit, 1024pt, single output, 1 parallel fft engine, burst, 3 mults/5 adders fft function 1056 5 3 235.07 195.0 163.02 mhz 8-bit, 1024pt, single output, 1 parallel fft engine, burst, 4 mults/2 adders fft function 1006 5 4 235.07 195.0 163.02 mhz 8-bit, 1024 pt, single output, 2 parallel fft engines, burst, 3 mults/5 adders fft function 1857 10 6 200.0 195.0 163.02 mhz 8-bit, 1024 pt, single output, 2 parallel fft engines, burst, 4 mults/2 adders fft function 1757 10 8 200.0 195.0 163.02 mhz 8-bit, 1024pt, quad output, 1 parallel fft engine, burst, 3 mults/5 adders fft function 2550 10 9 235.07 195.0 163.02 mhz table 5?15. cyclone ii performance (part 2 of 4) note (1) applications resources used performance les m4k memory blocks dsp blocks -6 speed grade -7 speed grade -8 speed grade units
altera corporation 5?17 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications larger designs 8-bit, 1024 pt, quad output, 1 parallel fft engine, burst, 4 mults/2 adders fft function 2400 10 12 235.07 195.0 163.02 mhz 8-bit, 1024 pt, quad output, 2 parallel fft engines, burst, 3 mults/5 adders fft function 4343 14 18 200.0 195.0 163.02 mhz 8-bit, 1024 pt, quad output, 2 parallel fft engines, burst, 4 mults/2 adders fft function 4043 14 24 200.0 195.0 163.02 mhz 8-bit, 1024 pt, quad output, 4 parallel fft engines, burst, 3 mults/5 adders fft function 7496 28 36 200.0 195.0 163.02 mhz 8-bit, 1024 pt, quad output, 4 parallel fft engines, burst, 4 mults/2 adders fft function 6896 28 48 200.0 195.0 163.02 mhz 8-bit, 1024 pt, quad output, 1 parallel fft engine, buffered burst, 3 mults/5 adders fft function 2934 18 9 235.07 195.0 163.02 mhz 8-bit, 1024 pt, quad output, 1 parallel fft engines, buffered burst, 4 mults/2 adders fft function 2784 18 12 235.07 195.0 163.02 mhz 8-bit, 1024 pt, quad output, 2 parallel fft engines, buffered burst, 3 mults/5 adders fft function 4720 30 18 200.0 195.0 163.02 mhz 8-bit, 1024 pt, quad output, 2 parallel fft engines, buffered burst, 4 mults/2 adders fft function 4420 30 24 200.0 195.0 163.02 mhz table 5?15. cyclone ii performance (part 3 of 4) note (1) applications resources used performance les m4k memory blocks dsp blocks -6 speed grade -7 speed grade -8 speed grade units
5?18 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications internal timing see tables 5?16 through 5?19 for the internal timing parameters. larger designs 8-bit, 1024 pt, quad output, 4 parallel fft engines, buffered burst, 3 mults/5 adders fft function 8053 60 36 200.0 195.0 163.02 mhz 8-bit, 1024 pt, quad output, 4 parallel fft engines, buffered burst, 4 mults/2 adders fft function 7453 60 48 200.0 195.0 163.02 mhz notes to table 5?15 : (1) these design performance numbers were obta ined using the quartus ii software version 6.0. (2) this application uses regi stered inputs and outputs. (3) this application uses registered multiplier input and output stages within the dsp block. (4) this application uses the same clock source for both a and b ports. (5) this application uses independent clock sources for a and b ports. (6) this application uses pll clock outputs that are globa lly routed to connect and drive m4k clock ports. use of non-pll clock sources or local routing to drive m4k clock ports may result in lower performance numbers than shown here. refer to the quartus ii timing report for actual performance numbers. table 5?15. cyclone ii performance (part 4 of 4) note (1) applications resources used performance les m4k memory blocks dsp blocks -6 speed grade -7 speed grade -8 speed grade units table 5?16. le_ff internal timing microparameters (part 1 of 2) parameter -6 speed grade (1) -7 speed grade (2) -8 speed grade (2) unit min max min max min max tsu -36 -38 -40 ps -40 ps th 266 286 306 ps 306 ps tco 141 250 141 277 135 304 ps 141 ps tclr 191 217 244 ps 244 ps tpre 191 217 244 ps 244 ps
altera corporation 5?19 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications tclkl 1000 1111 1242 ps 1242 ps tclkh 1000 1111 1242 ps 1242 ps tlut 180 438 180 545 172 651 ps 180 ps notes to table 5?16 : (1) for the -6 and -7 speed grades, the minimum timing is for the commercial temperature grade. only -8 speed grade devices offer the industrial temperature grade. (2) for the -8 speed grade, the first number is the mi nimum timing parameter for indu strial devices. the second number is the minimum timing pa rameter for commercial devices. table 5?17. ioe internal timing microparameters (part 1 of 2) parameter -6 speed grade (1) -7 speed grade (2) -8 speed grade (2) unit min max min max min max tsu 76 89 101 ps 101 ps th 88 97 106 ps 106 ps tco 99 155 99 171 95 187 ps 99 ps tpin2combout_r 384 762 384 784 366 855 ps 384 ps tpin2combout_c 385 760 385 783 367 854 ps 385 ps tcombin2pin_r 1344 2490 1344 2689 1280 2887 ps 1344 ps tcombin2pin_c 1418 2622 1418 2831 1352 3041 ps 1418 ps tclr 137 151 165 ps 165 ps tpre 192 212 233 ps 233 ps table 5?16. le_ff internal timing microparameters (part 2 of 2) parameter -6 speed grade (1) -7 speed grade (2) -8 speed grade (2) unit min max min max min max
5?20 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications tclkl 1000 1111 1242 ps 1242 ps tclkh 1000 1111 1242 ps 1242 ps notes to table 5?17 : (1) for the -6 and -7 speed grades, the minimum timing is for the commercial temperature grade. only -8 speed grade devices offer the industrial temperature grade. (2) for the -8 speed grade, the first number is the mi nimum timing parameter for indu strial devices. the second number is the minimum timing pa rameter for commercial devices. table 5?18. dsp block internal timing microparameters (part 1 of 2) parameter -6 speed grade (1) -7 speed grade (1) -8 speed grade (2) unit min max min max min max tsu 475462ps 62 ps th 110 111 113 ps 113 ps tco 000000ps 0ps tinreg2pipe9 652 1379 652 1872 621 2441 ps 652 ps tinreg2pipe18 652 1379 652 1872 621 2441 ps 652 ps tpipe2outreg 47 104 47 142 45 185 ps 47 ps tpd9 529 2470 529 3353 505 4370 ps 529 ps tpd18 425 2903 425 3941 406 5136 ps 425 ps tclr 2686 3129 3572 ps 3572 ps tclkl 1923 2307 2769 ps 2769 ps table 5?17. ioe internal timing microparameters (part 2 of 2) parameter -6 speed grade (1) -7 speed grade (2) -8 speed grade (2) unit min max min max min max
altera corporation 5?21 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications tclkh 1923 2307 2769 ps 2769 ps notes to table 5?18 : (1) for the -6 and -7 speed grades, the minimum timing is for the commercial temperature grade. only -8 speed grade devices offer the industrial temperature grade. (2) for the -8 speed grade, the first number is the mi nimum timing parameter for indu strial devices. the second number is the minimum timing pa rameter for commercial devices. table 5?19. m4k block internal timing microparameters (part 1 of 2) parameter -6 speed grade (1) -7 speed grade (1) -8 speed grade (2) unit min max min max min max tm4krc 2387 3764 2387 4248 2275 4736 ps 2387 ps tm4kweresu 35 40 46 ps 46 ps tm4kwereh 234 250 267 ps 267 ps tm4kbesu 35 40 46 ps 46 ps tm4kbeh 234 250 267 ps 267 ps tm4kdataasu 35 40 46 ps 46 ps tm4kdataah 234 250 267 ps 267 ps tm4kaddrasu 35 40 46 ps 46 ps tm4kaddrah 234 250 267 ps 267 ps tm4kdatabsu 35 40 46 ps 46 ps tm4kdatabh 234 250 267 ps 267 ps table 5?18. dsp block internal timing microparameters (part 2 of 2) parameter -6 speed grade (1) -7 speed grade (1) -8 speed grade (2) unit min max min max min max
5?22 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications cyclone ii clock timing parameters see tables 5?20 through 5?34 for cyclone ii clock timing parameters. tm4kraddrbsu 35 40 46 ps 46 ps tm4kraddrbh 234 250 267 ps 267 ps tm4kdataco1 466 724 466 826 445 930 ps 466 ps tm4kdataco2 2345 3680 2345 4157 2234 4636 ps 2345 ps tm4kclkh 1923 2307 2769 ps 2769 ps tm4kclkl 1923 2307 2769 ps 2769 ps tm4kclr 191 217 244 ps 244 ps notes to table 5?19 : (1) for the -6 and -7 speed grades, the minimum timing is for the commercial temperature grade. only -8 speed grade devices offer the industrial temperature grade. (2) for the -8 speed grade, the first number is the mi nimum timing parameter for indu strial devices. the second number is the minimum timing pa rameter for commercial devices. table 5?19. m4k block internal timing microparameters (part 2 of 2) parameter -6 speed grade (1) -7 speed grade (1) -8 speed grade (2) unit min max min max min max table 5?20. cyclone ii clock timing parameters symbol parameter t cin delay from clock pad to i/o input register t cout delay from clock pad to i/o output register t pllcin delay from pll inclk pad to i/o input register t pllcout delay from pll inclk pad to i/o output register
altera corporation 5?23 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications ep2c5 clock timing parameters tables 5?21 and 5?22 show the clock timing parameters for ep2c5 devices. ep2c 8 clock timing parameters tables 5?23 and 5?24 show the clock timing parameters for ep2c8 devices. table 5?21. ep2c5 column pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.283 1.343 2.329 2.484 2.688 ns tcout 1.297 1.358 2.363 2.516 2.717 ns tpllcin -0.188 -0.201 0.076 0.038 0.052 ns tpllcout -0.174 -0.186 0.11 0.07 0.081 ns table 5?22. ep2c5 row pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.212 1.267 2.210 2.351 2.540 ns tcout 1.214 1.269 2.226 2.364 2.548 ns tpllcin -0.259 -0.277 -0.043 -0.095 -0.096 ns tpllcout -0.257 -0.275 -0.027 -0.082 -0.088 ns table 5?23. ep2c8 column pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.339 1.404 2.405 2.565 2.774 ns tcout 1.353 1.419 2.439 2.597 2.803 ns tpllcin -0.193 -0.204 0.055 0.015 0.026 ns tpllcout -0.179 -0.189 0.089 0.047 0.055 ns
5?24 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications ep2c15 clock timing parameters tables 5?25 and 5?26 show the clock timing parameters for ep2c15 devices. table 5?24. ep2c8 row pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.256 1.314 2.270 2.416 2.606 ns tcout 1.258 1.316 2.286 2.429 2.614 ns tpllcin -0.276 -0.294 -0.08 -0.134 -0.142 ns tpllcout -0.274 -0.292 -0.064 -0.121 -0.134 ns table 5?25. ep2c15 column pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.621 1.698 2.590 2.766 2.989 ns tcout 1.635 1.713 2.624 2.798 3.018 ns tpllcin -0.351 -0.372 0.045 0.008 0.016 ns tpllcout -0.337 -0.357 0.079 0.04 0.045 ns table 5?26. ep2c15 row pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.542 1.615 2.490 2.651 2.866 ns tcout 1.544 1.617 2.506 2.664 2.874 ns tpllcin -0.424 -0.448 -0.057 -0.107 -0.107 ns tpllcout -0.422 -0.446 -0.041 -0.094 -0.099 ns
altera corporation 5?25 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications ep2c20 clock timing parameters tables 5?27 and 5?28 show the clock timing parameters for ep2c20 devices. ep2c35 clock timing parameters tables 5?29 and 5?30 show the clock timing parameters for ep2c35 devices. table 5?27. ep2c20 column pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.621 1.698 2.590 2.766 2.989 ns tcout 1.635 1.713 2.624 2.798 3.018 ns tpllcin -0.351 -0.372 0.045 0.008 0.016 ns tpllcout -0.337 -0.357 0.079 0.04 0.045 ns table 5?28. ep2c20 row pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.542 1.615 2.490 2.651 2.866 ns tcout 1.544 1.617 2.506 2.664 2.874 ns tpllcin -0.424 -0.448 -0.057 -0.107 -0.107 ns tpllcout -0.422 -0.446 -0.041 -0.094 -0.099 ns table 5?29. ep2c35 column pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.499 1.569 2.652 2.878 3.155 ns tcout 1.513 1.584 2.686 2.910 3.184 ns tpllcin -0.026 -0.032 0.272 0.316 0.41 ns tpllcout -0.012 -0.017 0.306 0.348 0.439 ns
5?26 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications ep2c50 clock timing parameters tables 5?31 and 5?32 show the clock timing parameters for ep2c50 devices. ep2c70 clock timing parameters tables 5?33 and 5?34 show the clock timing parameters for ep2c70 devices . table 5?30. ep2c35 row pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.410 1.476 2.514 2.724 2.986 ns tcout 1.412 1.478 2.530 2.737 2.994 ns tpllcin -0.117 -0.127 0.134 0.162 0.241 ns tpllcout -0.115 -0.125 0.15 0.175 0.249 ns table 5?31. ep2c50 column pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.575 1.651 2.759 2.940 3.174 ns tcout 1.589 1.666 2.793 2.972 3.203 ns tpllcin -0.149 -0.158 0.113 0.075 0.089 ns tpllcout -0.135 -0.143 0.147 0.107 0.118 ns table 5?32. ep2c50 row pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.463 1.533 2.624 2.791 3.010 ns tcout 1.465 1.535 2.640 2.804 3.018 ns tpllcin -0.261 -0.276 -0.022 -0.074 -0.075 ns tpllcout -0.259 -0.274 -0.006 -0.061 -0.067 ns
altera corporation 5?27 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?33. ep2c70 column pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.575 1.651 2.914 3.105 3.174 ns tcout 1.589 1.666 2.948 3.137 3.203 ns tpllcin -0.149 -0.158 0.27 0.268 0.089 ns tpllcout -0.135 -0.143 0.304 0.3 0.118 ns table 5?34. ep2c70 row pins global clock timing parameters parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial tcin 1.463 1.533 2.753 2.927 3.010 ns tcout 1.465 1.535 2.769 2.940 3.018 ns tpllcin -0.261 -0.276 0.109 0.09 -0.075 ns tpllcout -0.259 -0.274 0.125 0.103 -0.067 ns
5?28 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications clock network skew adders table 5?35 shows the clock network specifications. table 5?35. clock network specifications name description max unit clock skew adder ep2c5, ep2c8 (1) inter-clock network, same bank 88 ps inter-clock network, same side and entire chip 88 ps clock skew adder ep2c15, ep2c20, ep2c35, ep2c50, ep2c70 (1) inter-clock network, same bank 118 ps inter-clock network, same side and entire chip 138 ps note to table 5?35 : (1) this is in addition to intra-clock network skew, which is modeled in the quartus ii software.
altera corporation 5?29 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications ioe programmable delay see table 5?36 and 5?37 for ioe programmable delay. table 5?36. cyclone ii ioe programm able delay on column pins notes (1) , (2) parameter paths affected number of settings fast corner (3) -6 speed grade -7 speed grade -8 speed grade unit min offset max offset min offset max offset min offset max offset min offset max offset input delay from pin to internal cells pad -> i/o dataout to core 7 0 2233 0 3827 0 4088 0 4349 ps 0 2344 ps input delay from pin to input register pad -> i/o input register 8 0 2656 0 4555 0 4748 0 4940 ps 0 2788 ps delay from output register to output pin i/o output register -> pad 2 0 303 0 563 0 617 0 670 ps 0 318 ps notes to table 5?36 : (1) the incremental values for the settings are generally linear. for exact values of each setting, please use the latest version of quartus ii software. (2) the minimum and maximum of fset timing numbers are in reference to setting "0" as available in the quartus ii software. (3) the first number is the fast corner timing parameter for industr ial devices. the second number is the fast corner timing parameter for commercial devices. table 5?37. cyclone ii ioe programmable delay on row pins (part 1 of 2) notes (1) , (2) parameter paths affected number of settings fast corner (3) -6 speed grade -7 speed grade -8 speed grade unit min offset max offset min offset max offset min offset max offset min offset max offset input delay from pin to internal cells pad -> i/o dataout to core 7 0 2240 0 3776 0 4033 0 4290 ps 0 2352 ps input delay from pin to input register pad -> i/o input register 8 0 2669 0 4482 0 4671 0 4859 ps 0 2802 ps
5?30 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications default capacitive loading of different i/o standards see table 5?38 for default capacitive loading of different i/o standards. delay from output register to output pin i/o output register - > pad 2 0 308 0 572 0 626 0 682 ps 0 324 ps notes to table 5?37 : (1) the incremental values for the settings are generally linear. for exact values of each setting, please use the latest version of quartus ii software. (2) the minimum and maximum of fset timing numbers are in reference to se tting "0" as available in the quartus ii software. (3) the first number is the fast corner timing parameter for industr ial devices. the second number is the fast corner timing parameter for commercial devices. table 5?37. cyclone ii ioe programmable delay on row pins (part 2 of 2) notes (1) , (2) parameter paths affected number of settings fast corner (3) -6 speed grade -7 speed grade -8 speed grade unit min offset max offset min offset max offset min offset max offset min offset max offset table 5?38. default loading of different i/o standards for cyclone ii (part 1 of 2) i/o standard capacitive load unit lv t t l 0 p f lv c m o s 0 p f 2.5v 0 pf 1.8v 0 pf 1.5v 0 pf pci 10 pf pci-x 10 pf sstl_2_class_i 0 pf sstl_2_class_ii 0 pf sstl_18_class_i 0 pf sstl_18_class_ii 0 pf 1.5v_hstl_class_i 0 pf 1.5v_hstl_class_ii 0 pf 1.8v_hstl_class_i 0 pf 1.8v_hstl_class_ii 0 pf differential_sstl_2_class_i 0 pf
altera corporation 5?31 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications i/o delays see tables 5?39 through 5?43 for i/o delays. differential_sstl_2_class_ii 0 pf differential_sstl_18_class_i 0 pf differential_sstl_18_class_ii 0 pf 1.5v_differential_hstl_class_i 0 pf 1.5v_differential_hstl_class_ii 0 pf 1.8v_differential_hstl_class_i 0 pf 1.8v_differential_hstl_class_ii 0 pf lv d s 0 p f 1.2v_hstl 0 pf 1.2v_differential_hstl 0 pf table 5?39. i/o delay parameters symbol parameter t dip delay from i/o datain to output pad t op delay from i/o output register to output pad t pcout delay from input pad to i/o dataout to core t pi delay from input pad to i/o input register table 5?38. default loading of different i/o standards for cyclone ii (part 2 of 2) i/o standard capacitive load unit table 5?40. cyclone ii i/o input delay for column pins (part 1 of 3) i/o standard parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial lvttl tpi 581 609 1222 1228 1282 ps tpcout 367 385 760 783 854 ps 2.5v tpi 624 654 1192 1238 1283 ps tpcout 410 430 730 793 855 ps 1.8v tpi 725 760 1372 1428 1484 ps tpcout 511 536 910 983 1056 ps
5?32 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications 1.5v tpi 790 828 1439 1497 1556 ps tpcout 576 604 977 1052 1128 ps lvcmos tpi 581 609 1222 1228 1282 ps tpcout 367 385 760 783 854 ps sstl_2_class_i tpi 533 558 990 1015 1040 ps tpcout 319 334 528 570 612 ps sstl_2_class_ii tpi 533 558 990 1015 1040 ps tpcout 319 334 528 570 612 ps sstl_18_class_i tpi 577 605 1027 1035 1045 ps tpcout 363 381 565 590 617 ps sstl_18_class_ii tpi 577 605 1027 1035 1045 ps tpcout 363 381 565 590 617 ps 1.5v_hstl_class_i tpi 589 617 1145 1176 1208 ps tpcout 375 393 683 731 780 ps 1.5v_hstl_class_ii tpi 589 617 1145 1176 1208 ps tpcout 375 393 683 731 780 ps 1.8v_hstl_class_i tpi 577 605 1027 1035 1045 ps tpcout 363 381 565 590 617 ps 1.8v_hstl_class_ii tpi 577 605 1027 1035 1045 ps tpcout 363 381 565 590 617 ps differential_sstl_2_class_i tpi 533 558 990 1015 1040 ps tpcout 319 334 528 570 612 ps differential_sstl_2_class_ii tpi 533 558 990 1015 1040 ps tpcout 319 334 528 570 612 ps differential_sstl_18_class_i tpi 577 605 1027 1035 1045 ps tpcout 363 381 565 590 617 ps differential_sstl_18_class_ii tpi 577 605 1027 1035 1045 ps tpcout 363 381 565 590 617 ps 1.8v_differential_hstl_class_ i tpi 577 605 1027 1035 1045 ps tpcout 363 381 565 590 617 ps 1.8v_differential_hstl_class_ ii tpi 577 605 1027 1035 1045 ps tpcout 363 381 565 590 617 ps table 5?40. cyclone ii i/o input delay for column pins (part 2 of 3) i/o standard parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial
altera corporation 5?33 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications 1.5v_differential_hstl_class_ i tpi 589 617 1145 1176 1208 ps tpcout 375 393 683 731 780 ps 1.5v_differential_hstl_class_ ii tpi 589 617 1145 1176 1208 ps tpcout 375 393 683 731 780 ps lvds tpi 623 653 1072 1075 1078 ps tpcout 409 429 610 630 650 ps 1.2v_hstl tpi 570 597 1263 1324 1385 ps tpcout 356 373 801 879 957 ps 1.2v_differential_hstl tpi 570 597 1263 1324 1385 ps tpcout 356 373 801 879 957 ps table 5?41. cyclone ii i/o input dela y for row pins (part 1 of 2) i/o standard parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial lvttl tpi 583 611 1129 1160 1240 ps tpcout 366 384 762 784 855 ps 2.5v tpi 629 659 1099 1171 1244 ps tpcout 412 432 732 795 859 ps 1.8v tpi 729 764 1278 1360 1443 ps tpcout 512 537 911 984 1058 ps 1.5v tpi 794 832 1345 1429 1513 ps tpcout 577 605 978 1053 1128 ps lvcmos tpi 583 611 1129 1160 1240 ps tpcout 366 384 762 784 855 ps sstl_2_class_i tpi 536 561 896 947 998 ps tpcout 319 334 529 571 613 ps sstl_2_class_ii tpi 536 561 896 947 998 ps tpcout 319 334 529 571 613 ps sstl_18_class_i tpi 581 609 933 967 1004 ps tpcout 364 382 566 591 619 ps table 5?40. cyclone ii i/o input delay for column pins (part 3 of 3) i/o standard parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial
5?34 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications sstl_18_class_ii tpi 581 609 933 967 1004 ps tpcout 364 382 566 591 619 ps 1.5v_hstl_class_i tpi 593 621 1051 1109 1167 ps tpcout 376 394 684 733 782 ps 1.5v_hstl_class_ii tpi 593 621 1051 1109 1167 ps tpcout 376 394 684 733 782 ps 1.8v_hstl_class_i tpi 581 609 933 967 1004 ps tpcout 364 382 566 591 619 ps 1.8v_hstl_class_ii tpi 581 609 933 967 1004 ps tpcout 364 382 566 591 619 ps differential_sstl_2_class_i tpi 536 561 896 947 998 ps tpcout 319 334 529 571 613 ps differential_sstl_2_class_ii tpi 536 561 896 947 998 ps tpcout 319 334 529 571 613 ps differential_sstl_18_class_i tpi 581 609 933 967 1004 ps tpcout 364 382 566 591 619 ps differential_sstl_18_class_ii tpi 581 609 933 967 1004 ps tpcout 364 382 566 591 619 ps 1.8v_differential_hstl_class_i tpi 581 609 933 967 1004 ps tpcout 364 382 566 591 619 ps 1.8v_differential_hstl_class_i i tpi 581 609 933 967 1004 ps tpcout 364 382 566 591 619 ps 1.5v_differential_hstl_class_i tpi 593 621 1051 1109 1167 ps tpcout 376 394 684 733 782 ps 1.5v_differential_hstl_class_i i tpi 593 621 1051 1109 1167 ps tpcout 376 394 684 733 782 ps lvds tpi 651 682 1036 1075 1113 ps tpcout 434 455 669 699 728 ps pci tpi 595 623 1113 1156 1232 ps tpcout 378 396 746 780 847 ps pci-x tpi 595 623 1113 1156 1232 ps tpcout 378 396 746 780 847 ps table 5?41. cyclone ii i/o input dela y for row pins (part 2 of 2) i/o standard parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial
altera corporation 5?35 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?42. cyclone ii i/o output dela y for column pins (part 1 of 5) i/o standard drive strength parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial lvttl 4ma top 1524 1599 2903 3125 3348 ps tdip 1656 1738 3073 3319 3567 ps 8ma top 1343 1409 2670 2866 3061 ps tdip 1475 1548 2840 3060 3280 ps 12ma top 1287 1350 2547 2735 2924 ps tdip 1419 1489 2717 2929 3143 ps 16ma top 1239 1299 2478 2665 2851 ps tdip 1371 1438 2648 2859 3070 ps 20ma top 1228 1288 2456 2641 2827 ps tdip 1360 1427 2626 2835 3046 ps 24ma (1) top 1220 1279 2452 2637 2822 ps tdip 1352 1418 2622 2831 3041 ps lvcmos 4ma top 1346 1412 2509 2695 2880 ps tdip 1478 1551 2679 2889 3099 ps 8ma top 1240 1300 2473 2660 2847 ps tdip 1372 1439 2643 2854 3066 ps 12ma top 1221 1280 2428 2613 2797 ps tdip 1353 1419 2598 2807 3016 ps 16ma top 1203 1262 2403 2587 2772 ps tdip 1335 1401 2573 2781 2991 ps 20ma top 1194 1252 2378 2562 2745 ps tdip 1326 1391 2548 2756 2964 ps 24ma (1) top 1192 1250 2382 2566 2749 ps tdip 1324 1389 2552 2760 2968 ps 2.5v 4ma top 1208 1267 2478 2614 2750 ps tdip 1340 1406 2648 2808 2969 ps 8ma top 1190 1248 2307 2434 2561 ps tdip 1322 1387 2477 2628 2780 ps 12ma top 1154 1210 2192 2314 2437 ps tdip 1286 1349 2362 2508 2656 ps 16ma (1) top 1140 1195 2152 2263 2382 ps tdip 1272 1334 2322 2457 2601 ps
5?36 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications 1.8v 2ma top 1682 1765 3988 4279 4570 ps tdip 1814 1904 4158 4473 4789 ps 4ma top 1567 1644 3301 3538 3775 ps tdip 1699 1783 3471 3732 3994 ps 6ma top 1475 1547 2993 3195 3398 ps tdip 1607 1686 3163 3389 3617 ps 8ma top 1451 1522 2882 3074 3266 ps tdip 1583 1661 3052 3268 3485 ps 10ma top 1438 1508 2853 3041 3230 ps tdip 1570 1647 3023 3235 3449 ps 12ma (1) top 1438 1508 2853 3041 3230 ps tdip 1570 1647 3023 3235 3449 ps 1.5v 2ma top 2083 2186 4477 4870 5263 ps tdip 2215 2325 4647 5064 5482 ps 4ma top 1793 1881 3649 3965 4281 ps tdip 1925 2020 3819 4159 4500 ps 6ma top 1770 1857 3527 3823 4119 ps tdip 1902 1996 3697 4017 4338 ps 8ma (1) top 1703 1787 3537 3827 4118 ps tdip 1835 1926 3707 4021 4337 ps sstl_2_class_i 8ma top 1196 1254 2388 2516 2645 ps tdip 1328 1393 2558 2710 2864 ps 12ma (1) top 1174 1231 2277 2401 2525 ps tdip 1306 1370 2447 2595 2744 ps sstl_2_class_ii 16ma top 1158 1214 2245 2365 2486 ps tdip 1290 1353 2415 2559 2705 ps 20ma top 1152 1208 2231 2351 2471 ps tdip 1284 1347 2401 2545 2690 ps 24ma (1) top 1152 1208 2225 2345 2465 ps tdip 1284 1347 2395 2539 2684 ps table 5?42. cyclone ii i/o output dela y for column pins (part 2 of 5) i/o standard drive strength parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial
altera corporation 5?37 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications sstl_18_class_i 6ma top 1472 1544 3140 3345 3549 ps tdip 1604 1683 3310 3539 3768 ps 8ma top 1469 1541 3086 3287 3489 ps tdip 1601 1680 3256 3481 3708 ps 10ma top 1466 1538 2980 3171 3361 ps tdip 1598 1677 3150 3365 3580 ps 12ma (1) top 1466 1538 2980 3171 3361 ps tdip 1598 1677 3150 3365 3580 ps sstl_18_class_ii 16ma top 1454 1525 2905 3088 3270 ps tdip 1586 1664 3075 3282 3489 ps 18ma (1) top 1453 1524 2900 3082 3264 ps tdip 1585 1663 3070 3276 3483 ps 1.8v_hstl_class_i 8ma top 1460 1531 3222 3424 3625 ps tdip 1592 1670 3392 3618 3844 ps 10ma top 1462 1534 3090 3279 3469 ps tdip 1594 1673 3260 3473 3688 ps 12ma (1) top 1462 1534 3090 3279 3469 ps tdip 1594 1673 3260 3473 3688 ps 1.8v_hstl_class_ii 16ma top 1449 1520 2936 3107 3278 ps tdip 1581 1659 3106 3301 3497 ps 18ma top 1450 1521 2924 3101 3279 ps tdip 1582 1660 3094 3295 3498 ps 20ma (1) top 1452 1523 2926 3096 3266 ps tdip 1584 1662 3096 3290 3485 ps 1.5v_hstl_class_i 8ma top 1779 1866 4292 4637 4981 ps tdip 1911 2005 4462 4831 5200 ps 10ma top 1784 1872 4031 4355 4680 ps tdip 1916 2011 4201 4549 4899 ps 12ma (1) top 1784 1872 4031 4355 4680 ps tdip 1916 2011 4201 4549 4899 ps 1.5v_hstl_class_ii 16ma (1) top 1750 1836 3844 4125 4406 ps tdip 1882 1975 4014 4319 4625 ps table 5?42. cyclone ii i/o output dela y for column pins (part 3 of 5) i/o standard drive strength parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial
5?38 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications differential_sstl_2_c lass_i 8ma top 1196 1254 2388 2516 2645 ps tdip 1328 1393 2558 2710 2864 ps 12ma (1) top 1174 1231 2277 2401 2525 ps tdip 1306 1370 2447 2595 2744 ps differential_sstl_2_c lass_ii 16ma top 1158 1214 2245 2365 2486 ps tdip 1290 1353 2415 2559 2705 ps 20ma top 1152 1208 2231 2351 2471 ps tdip 1284 1347 2401 2545 2690 ps 24ma (1) top 1152 1208 2225 2345 2465 ps tdip 1284 1347 2395 2539 2684 ps differential_sstl_18_ class_i 6ma top 1472 1544 3140 3345 3549 ps tdip 1604 1683 3310 3539 3768 ps 8ma top 1469 1541 3086 3287 3489 ps tdip 1601 1680 3256 3481 3708 ps 10ma top 1466 1538 2980 3171 3361 ps tdip 1598 1677 3150 3365 3580 ps 12ma (1) top 1466 1538 2980 3171 3361 ps tdip 1598 1677 3150 3365 3580 ps differential_sstl_18_ class_ii 16ma top 1454 1525 2905 3088 3270 ps tdip 1586 1664 3075 3282 3489 ps 18ma (1) top 1453 1524 2900 3082 3264 ps tdip 1585 1663 3070 3276 3483 ps 1.8v_differential_hstl _class_i 8ma top 1460 1531 3222 3424 3625 ps tdip 1592 1670 3392 3618 3844 ps 10ma top 1462 1534 3090 3279 3469 ps tdip 1594 1673 3260 3473 3688 ps 12ma (1) top 1462 1534 3090 3279 3469 ps tdip 1594 1673 3260 3473 3688 ps table 5?42. cyclone ii i/o output dela y for column pins (part 4 of 5) i/o standard drive strength parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial
altera corporation 5?39 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications 1.8v_differential_hstl _class_ii 16ma top 1449 1520 2936 3107 3278 ps tdip 1581 1659 3106 3301 3497 ps 18ma top 1450 1521 2924 3101 3279 ps tdip 1582 1660 3094 3295 3498 ps 20ma (1) top 1452 1523 2926 3096 3266 ps tdip 1584 1662 3096 3290 3485 ps 1.5v_differential_hstl _class_i 8ma top 1779 1866 4292 4637 4981 ps tdip 1911 2005 4462 4831 5200 ps 10ma top 1784 1872 4031 4355 4680 ps tdip 1916 2011 4201 4549 4899 ps 12ma (1) top 1784 1872 4031 4355 4680 ps tdip 1916 2011 4201 4549 4899 ps 1.5v_differential_hstl _class_ii 16ma (1) top 1750 1836 3844 4125 4406 ps tdip 1882 1975 4014 4319 4625 ps lvds - top 1258 1319 2243 2344 2445 ps tdip 1390 1458 2413 2538 2664 ps rsds - top 1258 1319 2243 2344 2445 ps tdip 1390 1458 2413 2538 2664 ps mini_lvds - top 1258 1319 2243 2344 2445 ps tdip 1390 1458 2413 2538 2664 ps simple_rsds - top 1221 1280 2258 2435 2612 ps tdip 1353 1419 2428 2629 2831 ps 1.2v_hstl - top 2403 2522 4635 5344 6053 ps tdip 2535 2661 4805 5538 6272 ps 1.2v_differential_hstl - top 2403 2522 4635 5344 6053 ps tdip 2535 2661 4805 5538 6272 ps note to table 5?42 : (1) this is the default setting in quartus ii software. table 5?42. cyclone ii i/o output dela y for column pins (part 5 of 5) i/o standard drive strength parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial
5?40 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications table 5?43. cyclone ii i/o output de lay for row pins (part 1 of 4) i/o standard drive strength parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial lvttl 4ma top 1343 1408 2539 2694 2891 ps tdip 1467 1540 2747 2931 3158 ps 8ma top 1198 1256 2411 2587 2762 ps tdip 1322 1388 2619 2824 3029 ps 12ma top 1156 1212 2282 2452 2620 ps tdip 1280 1344 2490 2689 2887 ps 16ma top 1124 1178 2286 2455 2624 ps tdip 1248 1310 2494 2692 2891 ps 20ma top 1112 1165 2245 2413 2580 ps tdip 1236 1297 2453 2650 2847 ps 24ma (1) top 1105 1158 2253 2422 2589 ps tdip 1229 1290 2461 2659 2856 ps lvcmos 4ma top 1200 1258 2231 2396 2561 ps tdip 1324 1390 2439 2633 2828 ps 8ma top 1125 1179 2260 2429 2597 ps tdip 1249 1311 2468 2666 2864 ps 12ma (1) top 1106 1159 2217 2383 2549 ps tdip 1230 1291 2425 2620 2816 ps 2.5v 4ma top 1126 1180 2350 2477 2604 ps tdip 1250 1312 2558 2714 2871 ps 8ma (1) top 1105 1158 2177 2296 2415 ps tdip 1229 1290 2385 2533 2682 ps
altera corporation 5?41 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications 1.8v 2ma top 1503 1576 3657 3927 4196 ps tdip 1627 1708 3865 4164 4463 ps 4ma top 1400 1468 3010 3226 3440 ps tdip 1524 1600 3218 3463 3707 ps 6ma top 1388 1455 2857 3050 3242 ps tdip 1512 1587 3065 3287 3509 ps 8ma top 1347 1412 2714 2897 3078 ps tdip 1471 1544 2922 3134 3345 ps 10ma top 1347 1412 2714 2897 3078 ps tdip 1471 1544 2922 3134 3345 ps 12ma (1) top 1332 1396 2678 2856 3034 ps tdip 1456 1528 2886 3093 3301 ps 1.5v 2ma top 1853 1943 4127 4492 4855 ps tdip 1977 2075 4335 4729 5122 ps 4ma top 1694 1776 3452 3747 4042 ps tdip 1818 1908 3660 3984 4309 ps 6ma (1) top 1694 1776 3452 3747 4042 ps tdip 1818 1908 3660 3984 4309 ps sstl_2_class _i 8ma top 1090 1142 2152 2268 2382 ps tdip 1214 1274 2360 2505 2649 ps 12ma (1) top 1097 1150 2131 2246 2360 ps tdip 1221 1282 2339 2483 2627 ps sstl_2_class _ii 16ma (1) top 1068 1119 2067 2177 2287 ps tdip 1192 1251 2275 2414 2554 ps sstl_18_clas s_i 6ma top 1371 1437 2828 3018 3206 ps tdip 1495 1569 3036 3255 3473 ps 8ma top 1365 1431 2832 3024 3215 ps tdip 1489 1563 3040 3261 3482 ps 10ma (1) top 1374 1440 2806 2990 3173 ps tdip 1498 1572 3014 3227 3440 ps table 5?43. cyclone ii i/o output de lay for row pins (part 2 of 4) i/o standard drive strength parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial
5?42 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications 1.8v_hstl_cla ss_i 8ma top 1364 1430 2853 3017 3184 ps tdip 1488 1562 3061 3254 3451 ps 10ma top 1332 1396 2842 3011 3179 ps tdip 1456 1528 3050 3248 3446 ps 12ma (1) top 1332 1396 2842 3011 3179 ps tdip 1456 1528 3050 3248 3446 ps 1.5v_hstl_cla ss_i 8ma (1) top 1657 1738 3642 3917 4191 ps tdip 1781 1870 3850 4154 4458 ps differential_ sstl_2_class _i 8ma top 1090 1142 2152 2268 2382 ps tdip 1214 1274 2360 2505 2649 ps 12ma (1) top 1097 1150 2131 2246 2360 ps tdip 1221 1282 2339 2483 2627 ps differential_ sstl_2_class _ii 16ma (1) top 1068 1119 2067 2177 2287 ps tdip 1192 1251 2275 2414 2554 ps differential_ sstl_18_clas s_i 6ma top 1371 1437 2828 3018 3206 ps tdip 1495 1569 3036 3255 3473 ps 8ma top 1365 1431 2832 3024 3215 ps tdip 1489 1563 3040 3261 3482 ps 10ma (1) top 1374 1440 2806 2990 3173 ps tdip 1498 1572 3014 3227 3440 ps 1.8v_differen tial_hstl_cla ss_i 8ma top 1364 1430 2853 3017 3184 ps tdip 1488 1562 3061 3254 3451 ps 10ma top 1332 1396 2842 3011 3179 ps tdip 1456 1528 3050 3248 3446 ps 12ma (1) top 1332 1396 2842 3011 3179 ps tdip 1456 1528 3050 3248 3446 ps 1.5v_differen tial_hstl_cla ss_i 8ma (1) top 1657 1738 3642 3917 4191 ps tdip 1781 1870 3850 4154 4458 ps lvds - top 1216 1275 2089 2184 2278 ps tdip 1340 1407 2297 2421 2545 ps rsds - top 1216 1275 2089 2184 2278 ps tdip 1340 1407 2297 2421 2545 ps table 5?43. cyclone ii i/o output de lay for row pins (part 3 of 4) i/o standard drive strength parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial
altera corporation 5?43 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications maximum input & output clock rate maximum clock toggle rate is de fined as the maximum frequency achievable for a clock type signal at an i/o pin. the i/o pin can be a regular i/o pin or a de dicated clock i/o pin. the maximum clock toggle rate is different from the maximum data bit rate. if the maximum clock toggle rate on a regular i/o pin is 300 mhz, the maximum data bit rate for dual data rate (ddr) could be potentially as high as 600 mbps on the same i/o pin. table 5?44 specifies the maximum in put clock toggle rates. table 5?45 specifies the maximum output cloc k toggle rates at default load. table 5?46 specifies the derating factors for the output clock toggle rate for non default load. to calculate the output toggle rate for a non default load, use this formula: the toggle rate for a non default load = 1000 / (1000/toggle rate at default load + derating factor * load value in pf/1000) for example, the output toggle rate at 0pf (default) load for sstl-18 class ii 18ma i/o standard is 270 mhz on a - 6 device column i/o pin. the derating factor is 29ps/pf. fo r a 10pf load, the toggle rate is calculated as: 1000 / (1000/270 + 29 10/1000) = 250 (mhz) mini_lvds - top 1216 1275 2089 2184 2278 ps tdip 1340 1407 2297 2421 2545 ps pci - top 989 1036 2070 2214 2358 ps tdip 1113 1168 2278 2451 2625 ps pci-x - top 989 1036 2070 2214 2358 ps tdip 1113 1168 2278 2451 2625 ps note to table 5?43 : (1) this is the default setting in quartus ii software. table 5?43. cyclone ii i/o output de lay for row pins (part 4 of 4) i/o standard drive strength parameter fast corner -6 speed grade -7 speed grade -8 speed grade units industrial commercial
5?44 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications tables 5?44 through 5?46 show the i/o toggle rates for cyclone ii devices. table 5?44. maximum input clock toggle ra te on cyclone ii devices (part 1 of 2) i/o standard maximum input clock toggle rate on cyclone ii devices (mhz) column i/o pins row i/o pins dedicated clock inputs -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade lvttl 450 405 360 450 405 360 420 380 340 2.5v 450 405 360 450 405 360 450 405 360 1.8v 450 405 360 450 405 360 450 405 360 1.5v 300 270 240 300 270 240 300 270 240 lvcmos 450 405 360 450 405 360 420 380 340 sstl_2_class_i 500 500 500 500 500 500 500 500 500 sstl_2_class_ii 500 500 500 500 500 500 500 500 500 sstl_18_class_i 500 500 500 500 500 500 500 500 500 sstl_18_class_ii 500 500 500 500 500 500 500 500 500 1.5v_hstl_class_i 500 500 500 500 500 500 500 500 500 1.5v_hstl_class_ii 500 500 500 500 500 500 500 500 500 1.8v_hstl_class_i 500 500 500 500 500 500 500 500 500 1.8v_hstl_class_ii 500 500 500 500 500 500 500 500 500 pci - - - 350 315 280 350 315 280 pci-x - - - 350 315 280 350 315 280 differential_sstl_2_class_i 500 500 500 500 500 500 500 500 500 differential_sstl_2_class_ ii 500 500 500 500 500 500 500 500 500 differential_sstl_18_class _i 500 500 500 500 500 500 500 500 500 differential_sstl_18_class _ii 500 500 500 500 500 500 500 500 500 1.8v_differential_hstl_ class_i 500 500 500 500 500 500 500 500 500 1.8v_differential_hstl_ class_ii 500 500 500 500 500 500 500 500 500 1.5v_differential_hstl_ class_i 500 500 500 500 500 500 500 500 500
altera corporation 5?45 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications 1.5v_differential_hstl_ class_ii 500 500 500 500 500 500 500 500 500 lvpecl - - - - - - 402 402 402 lvds 402 402 402 402 402 402 402 402 402 1.2v_hstl 110 90 80 - - - 110 90 80 1.2v_differential_hstl 110 90 80 - - - 110 90 80 table 5?45. maximum output clock toggle rate on cyclone ii devices (part 1 of 4) i/o standard drive strength maximum output clock toggle rate on cyclone ii devices (mhz) column i/o pins (1) row i/o pins (1) dedicated clock outputs -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade lvttl 4ma 120 100 80 120 100 80 120 100 80 8ma 200 170 140 200 170 140 200 170 140 12ma 280 230 190 280 230 190 280 230 190 16ma 290 240 200 290 240 200 290 240 200 20ma 330 280 230 330 280 230 330 280 230 24ma 360 300 250 360 300 250 360 300 250 lvcmos 4ma 250 210 170 250 210 170 250 210 170 8ma 280 230 190 280 230 190 280 230 190 12ma 310 260 210 310 260 210 310 260 210 16ma 320270220------ 20ma 350290240------ 24ma 370310250------ table 5?44. maximum input clock toggle ra te on cyclone ii devices (part 2 of 2) i/o standard maximum input clock toggle rate on cyclone ii devices (mhz) column i/o pins row i/o pins dedicated clock inputs -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade
5?46 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications 2.5v 4ma 180 150 120 180 150 120 180 150 120 8ma 280 230 190 280 230 190 280 230 190 12ma 440370300------ 16ma 450405350------ 1.8v 2ma 120 100 80 120 100 80 120 100 80 4ma 180 150 120 180 150 120 180 150 120 6ma 220 180 150 220 180 150 220 180 150 8ma 240 200 160 240 200 160 240 200 160 10ma 300 250 210 300 250 210 300 250 210 12ma 350 290 240 350 290 240 350 290 240 1.5v 2ma 806050806050806050 4ma 130 110 90 130 110 90 130 110 90 6ma 180 150 120 180 150 120 180 150 120 8ma 230190160------ sstl_2_class_ i 8ma 400 340 280 400 340 280 400 340 280 12ma 400 340 280 400 340 280 400 340 280 sstl_2_class_ ii 16ma 350 290 240 350 290 240 350 290 240 20ma 400340280------ 24ma 400340280------ sstl_18_ class_i 6ma 260 220 180 260 220 180 260 220 180 8ma 260 220 180 260 220 180 260 220 180 10ma 270 220 180 270 220 180 270 220 180 12ma 280230190------ sstl_18_ class_ii 16ma 260220180------ 18ma 270220180------ 1.8v_hstl_ class_i 8ma 260 220 180 260 220 180 260 220 180 10ma 300 250 210 300 250 210 300 250 210 12ma 320 270 220 320 270 220 320 270 220 table 5?45. maximum output clock toggle rate on cyclone ii devices (part 2 of 4) i/o standard drive strength maximum output clock toggle rate on cyclone ii devices (mhz) column i/o pins (1) row i/o pins (1) dedicated clock outputs -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade
altera corporation 5?47 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications 1.8v_hstl_ class_ii 16ma 230190160------ 18ma 240200160------ 20ma 250210170------ 1.5v_hstl_ class_i 8ma 210 170 140 210 170 140 210 170 140 10ma 220180150------ 12ma 230190160------ 1.5v_hstl_ class_ii 16ma 210170140------ differential_ sstl_2_class_ i 8ma 400 340 280 400 340 280 400 340 280 12ma 400 340 280 400 340 280 400 340 280 differential_ sstl_2_class_ ii 16ma 350 290 240 350 290 240 350 290 240 20ma 400340280------ 24ma 400340280------ differential_ sstl_18_class _i 6ma 260 220 180 260 220 180 260 220 180 8ma 260 220 180 260 220 180 260 220 180 10ma 270 220 180 270 220 180 270 220 180 12ma 280230190------ differential_ sstl_18_class _ii 16ma 260220180------ 18ma 270220180------ 1.8v_ differential_ hstl_class_i 8ma 260 220 180 260 220 180 260 220 180 10ma 300 250 210 300 250 210 300 250 210 12ma 320 270 220 320 270 220 320 270 220 1.8v_ differential_ hstl_class_ii 16ma 230190160------ 18ma 240200160------ 20ma 250210170------ 1.5v_ differential_ hstl_class_i 8ma 210 170 140 210 170 140 210 170 140 10ma 220180150------ 12ma 230190160------ table 5?45. maximum output clock toggle rate on cyclone ii devices (part 3 of 4) i/o standard drive strength maximum output clock toggle rate on cyclone ii devices (mhz) column i/o pins (1) row i/o pins (1) dedicated clock outputs -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade
5?48 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications 1.5v_ differential_ hstl_class_ii 16ma 210170140------ lvds - 400 340 280 400 340 280 400 340 280 rsds - 400 340 280 400 340 280 400 340 280 mini_lvds - 400 340 280 400 340 280 400 340 280 simple_rsds - 380 320 260 380 320 260 380 320 260 1.2v_hstl - 808080------ 1.2v_ differential_ hstl - 808080------ pci - - - - 350 315 280 350 315 280 pci-x - - - - 350 315 280 350 315 280 lvttl oct_25_ohms 360 300 250 360 300 250 360 300 250 lvcmos oct_25_ohms 360 300 250 360 300 250 360 300 250 2.5v oct_50_ohms 240 200 160 240 200 160 240 200 160 1.8v oct_50_ohms 290 240 200 290 240 200 290 240 200 sstl_2_class_ i oct_50_ohms 240 200 160 240 200 160 - - - sstl_18_class _i oct_50_ohms 290 240 200 290 240 200 - - - note to table 5?45 : (1) this is based on single data rate i/os. table 5?45. maximum output clock toggle rate on cyclone ii devices (part 4 of 4) i/o standard drive strength maximum output clock toggle rate on cyclone ii devices (mhz) column i/o pins (1) row i/o pins (1) dedicated clock outputs -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade
altera corporation 5?49 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?46. maximum output clock toggle rate derating factors (part 1 of 4) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade lvttl 4ma 438 439 439 338 362 387 338 362 387 8ma 306 321 336 267 283 299 267 283 299 12ma 139 179 220 193 198 202 193 198 202 16ma 145 158 172 139 147 156 139 147 156 20ma 657790747984747984 24ma 192021141822141822 lvcmos 4ma 298 305 313 197 205 214 197 205 214 8ma 190 205 219 112 118 125 112 118 125 12ma 43 72 101 27 31 35 27 31 35 16ma 8799110------ 20ma 364656------ 24ma 242527------ 2.5v 4ma 228 233 237 270 306 343 270 306 343 8ma 173 177 180 191 199 208 191 199 208 12ma 119121123------ 16ma 646566------ 1.8v 2ma 452 457 461 332 367 403 332 367 403 4ma 321 347 373 244 291 337 244 291 337 6ma 227 255 283 178 222 266 178 222 266 8ma 37 118 199 58 133 207 58 133 207 10ma 41 72 103 46 85 123 46 85 123 12ma 7 8 10132844132844 1.5v 2ma 738 764 789 540 604 669 540 604 669 4ma 499 518 536 300 354 408 300 354 408 6ma 261 271 282 60 103 146 60 103 146 8ma 222529------ sstl_2_class_ i 8ma 464749254056254056 12ma 676970234260234260
5?50 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications sstl_2_class_ ii 16ma 424345152942152942 20ma 414244------ 24ma 404243------ sstl_18_ class_i 6ma 202224464749464749 8ma 202224474951474951 10ma 202225232527232527 12ma 192326------ sstl_18_ class_ii 16ma 303336------ 18ma 292929------ 1.8v_hstl_ class_i 8ma 262829596163596163 10ma 464748656668656668 12ma 676767717172717172 1.8v_hstl_ class_ii 16ma 626568------ 18ma 596265------ 20ma 575962------ 1.5v_hstl_ class_i 8ma 404041283236283236 10ma 414242------ 12ma 434343------ 1.5v_hstl_ class_ii 16ma 182021------ differential_ sstl_2_class_ i 8ma 464749254056254056 12ma 676970234260234260 differential_ sstl_2_class_ ii 16ma 424345152942152942 20ma 414244------ 24ma 404243------ table 5?46. maximum output clock toggle rate derating factors (part 2 of 4) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade
altera corporation 5?51 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications differential_ sstl_18_class _i 6ma 202224464749464749 8ma 202224474951474951 10ma 202225232527232527 12ma 192326------ differential_ sstl_18_class _ii 16ma 303336------ 18ma 292929------ 1.8v_ differential_ hstl_class_i 8ma 262829596163596163 10ma 464748656668656668 12ma 676767717172717172 1.8v_ differential_ hstl_class_ii 16ma 626568------ 18ma 596265------ 20ma 575962------ 1.5v_ differential_ hstl_class_i 8ma 404041283236283236 10ma 414242------ 12ma 434343------ 1.5v_ differential_ hstl_class_ii 16ma 182021------ lvds - 111316111315111315 rsds - 111316111315111315 mini_lvds - 11 13 16 11 13 15 11 13 15 simple_rsds - 15 19 23 15 19 23 15 19 23 1.2v_hstl - 130132133------ 1.2v_ differential_ hstl - 130132133------ pci - - - - 99 120 142 99 120 142 pci-x - - - - 99 121 143 99 121 143 lvttl oct_25_ohms 13 14 14 21 27 33 21 27 33 table 5?46. maximum output clock toggle rate derating factors (part 3 of 4) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade
5?52 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications high speed i/o timing specifications the timing analysis for lvds, mi ni-lvds, and rsds is different compared to other i/o standards because the data communication is source-synchronous. you should also consider board skew, cable skew, and clock jitter in your calculation. this section provides details on the timing parameters for high-speed i/o standards in cyclone ii devices. table 5?47 defines the parameters of the timing diagram shown in figure 5?3 . lvcmos oct_25_ohms 13 14 14 21 27 33 21 27 33 2.5v oct_50_ohms 346 369 392 324 326 327 324 326 327 1.8v oct_50_ohms 198 203 209 202 203 204 202 203 204 sstl_2_class_ i oct_50_ohms 67 69 70 25 42 60 25 42 60 sstl_18_class _i oct_50_ohms 30 33 36 47 49 51 47 49 51 table 5?46. maximum output clock toggle rate derating factors (part 4 of 4) i/o standard drive strength maximum output clock toggle rate derating factors (ps/pf) column i/o pins row i/o pins dedicated clock outputs -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade -6 speed grade -7 speed grade -8 speed grade table 5?47. high-speed i/o timing definitions (part 1 of 2) parameter symbol description high-speed clock f hscklk high-speed receiver and transmitte r input and output clock frequency. duty cycle t duty duty cycle on high-speed transmitter output clock. high-speed i/o data rate hsiodr high-speed receiv er and transmitter input and output data rate. time unit interval tui tui = 1/hsiodr. channel-to-channel skew tccs the ti ming difference between the fastest and slowest output edges, including t co variation and clock skew. the clock is included in the tccs measurement. tccs = tui ? sw ? (2 rskm)
altera corporation 5?53 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications figure 5?3. high-speed i/o timing diagram figure 5?4 shows the high-speed i/o timing budget. sampling window sw the period of time during wh ich the data must be valid in order for you to capture it correctly. sampling window is the sum of the setup time, hold time, and jitter. the window of t su + t h is expected to be centered in the sampling window. sw = tui ? tccs ? (2 rskm) receiver input skew margin rskm rskm is defined by the total margin left after accounting for the sampling window and tccs. rskm = (tui ? sw ? tccs) / 2 input jitter (peak to peak) peak-to-pea k input jitter on high-speed plls. output jitter (peak to peak) peak-t o-peak output jitter on high-speed plls. signal rise time t rise low-to-high transmission time. signal fall time t fall high-to-low transmission time. lock time t lock lock time for high-speed trans mitter and receiver plls. table 5?47. high-speed i/o timing definitions (part 2 of 2) parameter symbol description sampling window (sw) time unit interval (tui) rskm tccs rskm tccs internal clock external input clock receiver input data
5?54 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications figure 5?4. high-speed i/o timing budget note (1) note to figure 5?4 : (1) the equation for the high-speed i/o timing budget is: period = tccs + rskm + sw + rskm. table 5?48 shows the rsds timing budg et for cyclone ii devices at 311 mbps. rsds is supported for tran smitting from cyclone ii devices. cyclone ii devices cannot receive rsds data because the devices are intended for applications where they will be driving display drivers. cyclone ii devices support a maximum rs ds data rate of 311 mbps using ddio registers. cyclone ii devices support rsds only in the commercial temperature range. internal clock period rskm 0.5 tccs rskm 0.5 tccs sw table 5?48. rsds transmitter timi ng specification (part 1 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max (1) min typ max (1) min typ max (1) f hsclk (input clock frequency) 10 10 155.5 10 155.5 10 155.5 mhz 8 10 155.5 10 155.5 10 155.5 mhz 7 10 155.5 10 155.5 10 155.5 mhz 4 10 155.5 10 155.5 10 155.5 mhz 2 10 155.5 10 155.5 10 155.5 mhz 1 10 311 10 311 10 311 mhz device operation in mbps 10 100 311 100 311 100 311 mbps 8 80 311 80 311 80 311 mbps 7 70 311 70 311 70 311 mbps 4 40 311 40 311 40 311 mbps 2 20 311 20 311 20 311 mbps 1 10 311 10 311 10 311 mbps t duty 45 55 45 55 45 55 %
altera corporation 5?55 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications in order to determine the transmitter timing requirements, rsds receiver timing requirements on the other end of the link must be taken into consideration. rsds receiver timing parameters are typically defined as t su and t h requirements. therefore, the transmitter timing parameter specifications are t co (minimum) and t co (maximum). refer to figure 5?4 for the timing budget. the ac timing requirements for rsds are shown in figure 5?5 . tccs 200 200 200 ps output jitter (peak to peak) 500 500 500 ps t rise 20?80%, c load = 5 pf 500 500 500 ps t fall 80?20%, c load = 5 pf 500 500 500 ps t lock 100 100 100 s note to table 5?48 : (1) these specifications are for a thre e-resistor rsds implementation. for si ngle-resistor rsds in 10 through 2 modes, the maximum data rate is 170 mbps and the co rresponding maximum input clock frequency is 85 mhz. for single-resistor rsds in 1 mode, the maximum data rate is 170 mbps and the maximum input clock frequency is 170 mhz. see chapter 11 for more inform ation on the different rsds implementations. table 5?48. rsds transmitter timi ng specification (part 2 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max (1) min typ max (1) min typ max (1)
5?56 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications figure 5?5. rsds transmitter cl ock to data relationship table 5?49 shows the mini-lvds transmitte r timing budget for cyclone ii devices at 311 mbps. cyclone ii devices can not receive mini-lvds data because the devices are intended for applications where they will be driving display drivers. a maximum mini-lvds data rate of 311 mbps is supported for cyclone ii devices using ddio registers. cyclone ii devices support mini-lvds only in the commercial temperature range. transmitter valid data transmitter valid data valid data total skew valid data t su (2 ns) t h (2 ns) channel-to-channel skew (1.68 ns) transmitter clock (5.88 ns) at transmitter tx_data[11..0] at receiver rx_data[11..0] table 5?49. mini-lvds transmitter ti ming specification (part 1 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max f hsclk (input clock frequency) 10 10 155.5 10 155.5 10 155.5 mhz 8 10 155.5 10 155.5 10 155.5 mhz 7 10 155.5 10 155.5 10 155.5 mhz 4 10 155.5 10 155.5 10 155.5 mhz 2 10 155.5 10 155.5 10 155.5 mhz 1 10 311 10 311 10 311 mhz
altera corporation 5?57 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications in order to determine the transmitte r timing requirements, mini-lvds receiver timing requirements on th e other end of the link must be taken into consideration. mini -lvds receiver timing parameters are typically defined as t su and t h requirements. therefore, the transmitter timing parameter specifications are t co (minimum) and t co (maximum). refer to figure 5?4 for the timing budget. the ac timing requirements for mini-lvds are shown in figure 5?6 . figure 5?6. mini-lvds transmitte r ac timing specification notes to figure 5?6 : (1) the data setup time, t su , is 0.225 tui. (2) the data hold time, t h , is 0.225 tui. device operation in mbps 10 100 311 100 311 100 311 mbps 8 80 311 80 311 80 311 mbps 7 70 311 70 311 70 311 mbps 4 40 311 40 311 40 311 mbps 2 20 311 20 311 20 311 mbps 1 10 311 10 311 10 311 mbps t duty 45 55 45 55 45 55 % tccs 200 200 200 ps output jitter (peak to peak) 500 500 500 ps t rise 20?80% 500 500 500 ps t fall 80?20% 500 500 500 ps t lock 100 100 100 s table 5?49. mini-lvds transmitter ti ming specification (part 2 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max t su (1) t h (2) tui t su (1) t h (2) lvdsclk[]n lvdsclk[]p lvds[]p lvds[]n
5?58 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications tables 5?50 and 5?51 show the lvds timing budget for cyclone ii devices. cyclone ii devices support lv ds receivers at data rates up to 805 mbps and lvds transmitters at data rates up to 640 mbps. table 5?50. lvds transmitter ti ming specification (part 1 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max (1) max (2) min typ max (1) max (2) min typ max (1) max (2) f hsclk (input clock fre- quency) 10 10 320 320 10 275 320 10 155.5 (4) 320 (6) mhz 8 10 320 320 10 275 320 10 155.5 (4) 320 (6) mhz 7 10 320 320 10 275 320 10 155.5 (4) 320 (6) mhz 4 10 320 320 10 275 320 10 155.5 (4) 320 (6) mhz 2 10 320 320 10 275 320 10 155.5 (4) 320 (6) mhz 1 10 402.5 402.5 10 402.5 402.5 10 402.5 ( 8 ) 402.5 ( 8 ) mhz hsiodr 10 100 640 640 100 550 640 100 311 (5) 550 (7) mbps 8 80 640 640 80 550 640 80 311 (5) 550 (7) mbps 7 70 640 640 70 550 640 70 311 (5) 550 (7) mbps 4 40 640 640 40 550 640 40 311 (5) 550 (7) mbps 2 20 640 640 20 550 640 20 311 (5) 550 (7) mbps 1 10 402.5 402.5 10 402.5 402.5 10 402.5 (9) 402.5 (9) mbps t duty 45 55 45 55 45 55 % 160 312.5 363.6 ps tccs (3) 200 200 200 ps output jitter (peak to peak) 500 500 550 (10) ps t rise 20?80% 150 200 250 150 200 250 150 200 250 (11) ps
altera corporation 5?59 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications t fall 80?20% 150 200 250 150 200 250 150 200 250 (11) ps t lock 100 100 100 (12) s notes to table 5?50 : (1) the maximum data rate that complies with duty cycle distortion of 45?55%. (2) the maximum data rate when taking duty cycle in abso lute ps into consideration that may not comply with 45?55% duty cycle distortion. if the downstream receiver can handle duty cycle distortion beyond the 45?55% range, you may use the higher data rate values from this column. yo u can calculate the duty cycle distortion as a percentage using the absolute ps value. for example, for a data rate of 640 mbps (ui = 1562.5 ps) and a t duty of 250 ps, the duty cycle distortion is t duty /(ui*2) *100% = 250 ps/(1562.5 *2) * 100% = 8%, which gives you a duty cycle distortion of 42-58%. (3) the tccs specification applies to the entire bank of lvds as long as the serdes logic is placed within the lab adjacent to the output pins. (4) for extended temperature devices, the maximum input clock frequency for 10 through 2 modes is 137.5 mhz. (5) for extended temperature device s, the maximum data rate for 10 through 2 modes is 275 mbps. (6) for extended temperatur e devices, the maximum input clock frequency for 10 through 2 modes is 200 mhz. (7) for extended temperature device s, the maximum data rate for 10 through 2 modes is 400 mbps. (8) for extended temperature devi ces, the maximum input clock frequency for 1 mode is 340 mhz. (9) for extended temperature de vices, the maximum data rate for 1 mode is 340 mbps. (10) for extended temperature de vices, the maximum output jitter (peak to peak) is 600 ps. (11) for extended temperature devices, the maximum t rise and t fall are 300 ps. (12) for extended temperat ure devices, the maximum lock time is 500 us. table 5?50. lvds transmitter ti ming specification (part 2 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max (1) max (2) min typ max (1) max (2) min typ max (1) max (2)
5?60 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications external memory inte rface specifications table 5?52 shows the dqs bus clock skew adder specifications. table 5?51. lvds receiver timing specification symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max f hsclk (input clock frequency) 10 10 402.5 10 320 10 320 (1) mhz 8 10 402.5 10 320 10 320 (1) mhz 7 10 402.5 10 320 10 320 (1) mhz 4 10 402.5 10 320 10 320 (1) mhz 2 10 402.5 10 320 10 320 (1) mhz 1 10 402.5 10 402.5 10 402.5 (3) mhz hsiodr 10 100 805 100 640 100 640 (2) mbps 8 80 805 80 640 80 640 (2) mbps 7 70 805 70 640 70 640 (2) mbps 4 40 805 40 640 40 640 (2) mbps 2 20 805 20 640 20 640 (2) mbps 1 10 402.5 10 402.5 10 402.5 (4) mbps sw 300 400 400 ps input jitter tolerance 500 500 550 ps t lock 100 100 100 (5) ps notes to table 5?51 : (1) for extended temperatur e devices, the maximum input clock frequency for x10 through x2 modes is 275 mhz. (2) for extended temperature device s, the maximum data rate for x10 through x2 modes is 550 mbps. (3) for extended temperature devi ces, the maximum input clock frequency for x1 mode is 340 mhz. (4) for extended temperature de vices, the maximum data rate for x1 mode is 340 mbps. (5) for extended temperat ure devices, the maximum lock time is 500 us. table 5?52. dqs bus clock skew adder specifications mode dqs clock skew adder unit 9 155 ps 18 190 ps note to table 5?52 : (1) this skew specification is the absolute maximum and minimum skew. for example, skew on a 9 dq group is 155 ps or 77.5 ps.
altera corporation 5?61 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications jtag timing specifications figure 5?7 shows the timing requirements for the jtag signals. figure 5?7. cyclone ii jtag waveform tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz
5?62 altera corporation cyclone ii device handbook, volume 1 february 2007 timing specifications table 5?53 shows the jtag timing parameters and values for cyclone ii devices. 1 cyclone ii devices must be within the first 17 devices in a jtag chain. all of these devices have the same jtag controller. if any of the cyclone ii devices are in the 18th or after they will fail configuration. this does not affect the signaltap ? ii logic analyzer. f for more information on jtag, see the ieee 1149.1 (jtag) boundary- scan testing for cyclone ii devices chapter in the cyclone ii handbook and jam programming & test language specification . table 5?53. cyclone ii jtag timing parameters & values symbol parameter min max unit t jcp tck clock period 40 ns t jch tck clock high time 20 ns t jcl tck clock low time 20 ns t jpsu jtag port setup time (2) 5ns t jph jtag port hold time 10 ns t jpco jtag port clock to output (2) 13 ns t jpzx jtag port high impedance to valid output (2) 13 ns t jpxz jtag port valid output to high impedance (2) 13 ns t jssu capture register setup time (2) 5ns t jsh capture register hold time 10 ns t jsco update register clock to output 25 ns t jszx update register high impedance to valid output 25 ns t jsxz update register valid output to high impedance 25 ns notes to table 5?53 : (1) this information is preliminary. (2) this specification is shown for 3.3-v lvttl/lvcmos and 2.5-v lvttl/lvcmos operation of the jtag pins. for 1.8-v lvttl/lvcmos and 1.5-v lvc mos, the jtag port and capture regi ster clock setup time is 3 ns and port clock to output time is 15 ns.
altera corporation 5?63 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications pll timing specifications table 5?54 describes the cyclone ii pll specifications when operating in the commercial junction temperature range (0 to 85 c), the industrial junction temperature range (- 40 to 100 c), and the extended temperature range (-40 to 125 c). follow the pll specifications for -8 speed grade devices when operating in the industrial or extended temperature range. table 5?54. pll specifications (part 1 of 2) note (1) symbol parameter min typ max unit f in input clock frequency (-6 speed grade) 10 (4) mhz input clock frequency (-7 speed grade) 10 (4) mhz input clock frequency (-8 speed grade) 10 (4) mhz f inpfd pfd input frequency (-6 speed grade) 10 402.5 mhz pfd input frequency (-7 speed grade) 10 402.5 mhz pfd input frequency (-8 speed grade) 10 402.5 mhz f induty input clock duty cycle 40 60 % t injitter (5) input clock period jitter 200 ps f out_ext (external clock output) pll output frequency (-6 speed grade) 10 (4) mhz pll output frequency (-7 speed grade) 10 (4) mhz pll output frequency (-8 speed grade) 10 (4) mhz f out (to global clock) pll output frequency (-6 speed grade) 10 500 mhz pll output frequency (-7 speed grade) 10 450 mhz pll output frequency (-8 speed grade) 10 402.5 mhz t outduty duty cycle for external clock output (when set to 50%) 45 55 % t jitter (p-p) (2) period jitter for external clock output f out_ext > 100 mhz 300 ps f out_ext 100 mhz 30 mui t lock time required to lock from end of device configuration 100 (6) s t pll_pserr accuracy of pll phase shift 60 ps
5?64 altera corporation cyclone ii device handbook, volume 1 february 2007 duty cycle distortion duty cycle distortion duty cycle distortion (dcd) describe s how much the falling edge of a clock is off from its idea l position. the ideal position is when both the clock high time (clkh) and the clock low time (clkl) equal half of the clock period (t), as shown in figure 5?8 . dcd is the deviation of the non-ideal falling edge from the ideal falling edge, such as d1 for the falling edge a and d2 for the falling edge b ( figure 5?8 ). the maximum dcd for a clock is the larger value of d1 and d2. figure 5?8. duty cycle distortion dcd expressed in absolution deriva tion, for example, d1 or d2 in figure 5?8 , is clock-period independent. dcd can also be expressed as a percentage, and the percentage number is clock-period dependent. dcd as a percentage is defined as: f vco (3) pll internal vco operating range 300 1,000 mhz t areset minimum pulse width on areset signal. 10 ns notes to table 5?54 : (1) these numbers are preliminary an d pending silicon characterization. (2) the t jitter specification for the pll[4..1]_out pins are dependent on the i/o pins in its vccio bank, how many of them are switching outputs, how much they toggle, an d whether or not they use programmable current strength. (3) if the vco post-scale counter = 2, a 300- to 500-mhz internal vco frequency is available. (4) this parameter is limited in quartus ii software by the i/o maximum frequency. the maximum i/o frequency is different for each i/o standard. (5) cyclone ii plls can track a spread-spectrum input clock that has an input jitter within 200 ps. (6) for extended temperat ure devices, the maximum lock time is 500 us. table 5?54. pll specifications (part 2 of 2) note (1) symbol parameter min typ max unit clkh = t/2 clkl = t/2 d1 d2 falling edge a ideal falling edge clock period (t) falling edge b
altera corporation 5?65 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications (t/2 ? d1) / t (the low percentage boundary) (t/2 + d2) / t (the high percentage boundary) dcd measurement techniques dcd is measured at an fpga output pin driven by registers inside the corresponding i/o element (ioe) block. when the ou tput is a single data rate signal (non-ddio), on ly one edge of the regist er input clock (positive or negative) triggers output transitions ( figure 5?9 ). therefore, any dcd present on the input clock signal or caused by the clock input buffer or different input i/o standard does no t transfer to the output signal. figure 5?9. dcd measurement technique for non-ddio (single-da ta rate) outputs however, when the output is a doub le data rate input/output (ddio) signal, both edges of the input clock signal (posit ive and negative) trigger output transitions ( figure 5?10 ). therefore, any dist ortion on the input clock and the input clock buff er affect the output dcd. dq dff clk output ioe
5?66 altera corporation cyclone ii device handbook, volume 1 february 2007 duty cycle distortion figure 5?10. dcd measurement technique for ddio (double-data rate) outputs when an fpga pll generates the inte rnal clock, the pll output clocks the ioe block. as the pll only monitors the positive edge of the reference clock input and internally re-creates the output cloc k signal, any dcd present on the reference clock is filt ered out. therefore, the dcd for a ddio output with pll in the clock path is better than the dcd for a ddio output without pll in the clock path. tables 5?55 through 5?58 give the maximum dcd in absolution derivation for different i/o standards on stratix ii devices. examples are also provided that show how to calculate dcd as a percentage. dq prn clrn dff input vcc clk output dq prn clrn dff v cc gnd 1 0 table 5?55. maximum dcd for single data outputs (sdr) on row i/o pins (part 1 of 2) notes (1) , (2) row i/o output standard c6 c7 c8 unit lvcmos 165 230 230 ps lvttl 195 255 255 ps 2.5-v 120 120 135 ps 1.8-v 115 115 175 ps 1.5-v 130 130 135 ps sstl-2 class i 60 90 90 ps sstl-2 class ii 65 75 75 ps sstl-18 class i 90 165 165 ps hstl-15 class i 145 145 205 ps hstl-18 class i 85 155 155 ps
altera corporation 5?67 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications here is an example for calculating the dcd as a percentage for a sdr output on a row i/o on a -6 device: if the sdr output i/o standard is sstl-2 class ii, the maximum dcd is 65 ps (see table x-x1). if the clock fr equency is 167 mhz, the clock period t is: t = 1/ f = 1 / 167 mhz = 6 ns = 6000 ps to calculate the dcd as a percentage: (t/2 ? dcd) / t = (6000 ps/2 ? 65 ps) / 6000 ps = 48.91% (for low boundary) (t/2 + dcd) / t = (6000 ps/2 + 65 ps) / 6000ps = 51.08% (for high boundary differential sstl-2 class i 60 90 90 ps differential sstl-2 class ii 65 75 75 ps differential sstl-18 class i 90 165 165 ps differential hstl-18 class i 85 155 155 ps differential hstl-15 class i 145 145 205 ps lvds 60 60 60 ps simple rsds 60 60 60 ps mini lvds 60 60 60 ps pci 195 255 255 ps pci-x 195 255 255 ps notes to ta b l e 5 ? 5 5 : (1) the dcd specification is characterized using the maximum drive strength available for each i/o standard. (2) numbers are applicable for both commercial and industrial devices. table 5?56. maximum dcd for sdr output on column i/o (part 1 of 2) notes (1) , (2) column i/o output standard c6 c7 c8 unit lvcmos 195 285 285 ps lvttl 210 305 305 ps table 5?55. maximum dcd for single data outputs (sdr) on row i/o pins (part 2 of 2) notes (1) , (2) row i/o output standard c6 c7 c8 unit
5?68 altera corporation cyclone ii device handbook, volume 1 february 2007 duty cycle distortion 2.5-v 140 140 155 ps 1.8-v 115 115 165 ps 1.5-v 745 745 770 ps sstl-2 class i 60 60 75 ps sstl-2 class ii 60 60 80 ps sstl-18 class i 60 130 130 ps sstl-18 class ii 60 135 135 ps hstl-18 class i 60 115 115 ps hstl-18 class ii 75 75 100 ps hstl-15 class i 150 150 150 ps hstl-15 class ii 135 135 155 ps differential sstl-2 class i 60 60 75 ps differential sstl-2 class ii 60 60 80 ps differential sstl-18 class i 60 130 130 ps differential sstl-18 class ii 60 135 135 ps differential hstl-18 class i 60 115 115 ps differential hstl-18 class ii 75 75 100 ps differential hstl-15 class i 150 150 150 ps differential hstl-15 class ii 135 135 155 ps lvds 60 60 60 ps simple rsds 60 70 70 ps mini-lvds 60 60 60 ps notes to ta b l e 5 ? 5 6 : (1) the dcd specification is characterized using the maximum drive strength available for each i/o standard. (2) numbers are applicable for both commercial and industrial devices. table 5?57. maximum for ddio output on row pins with pll in the clock path (part 1 of 2) notes (1) , (2) row pins with pll in the clock path c6 c7 c8 unit lvcmos 270 310 310 ps lvttl 285 305 335 ps 2.5-v 180 180 220 ps 1.8-v 165 175 205 ps table 5?56. maximum dcd for sdr output on column i/o (part 2 of 2) notes (1) , (2) column i/o output standard c6 c7 c8 unit
altera corporation 5?69 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications for ddio outputs, you can calculat e actual half period from the following equation: actual half period = ideal half period ? maximum dcd for example, if the ddr output i/ o standard is sstl-2 class ii, the maximum dcd for a -5 device is 155 ps (see table x-x3). if the clock frequency is 167 mhz, the half-clock period t/2 is: t/2 = 1/(2* f )= 1 /(2*167 mhz) = 3 ns = 3000 ps 1.5-v 280 280 280 ps sstl-2 class i 150 190 230 ps sstl-2 class ii 155 200 230 ps sstl-18 class i 180 240 260 ps hstl-18 class i 180 235 235 ps hstl-15 class i 205 220 220 ps differential sstl-2 class i 150 190 230 ps differential sstl-2 class ii 155 200 230 ps differential sstl-18 class i 180 240 260 ps differential hstl-18 class i 180 235 235 ps differential hstl-15 class i 205 220 220 ps lvds 95 110 120 ps simple rsds 100 155 155 ps mini lvds 95 110 120 ps pci 285 305 335 ps pci-x 285 305 335 ps notes to ta b l e 5 ? 5 7 : (1) the dcd specification is characterized using the maximum drive strength available for each i/o standard. (2) numbers are applicable for both commercial and industrial devices. table 5?57. maximum for ddio output on row pins with pll in the clock path (part 2 of 2) notes (1) , (2) row pins with pll in the clock path c6 c7 c8 unit
5?70 altera corporation cyclone ii device handbook, volume 1 february 2007 duty cycle distortion the actual half period is then = 3000 ps ? 155 ps = 2845 ps table 5?58. maximum dcd for ddio output on column i/o pins with pll in the clock path notes (1) , (2) column i/o pins in the clock path c6 c7 c8 unit lvcmos 285 400 445 ps lvttl 305 405 460 ps 2.5-v 175 195 285 ps 1.8-v 190 205 260 ps 1.5-v 605 645 645 ps sstl-2 class i 125 210 245 ps sstl-2 class ii 195 195 195 ps sstl-18 class i 130 240 245 ps sstl-18 class ii 135 270 330 ps hstl-18 class i 135 240 240 ps hstl-18 class ii 165 240 285 ps hstl-15 class i 220 335 335 ps hstl-15 class ii 190 210 375 ps differential sstl-2 class i 125 210 245 ps differential sstl-2 class ii 195 195 195 ps differential sstl-18 class i 130 240 245 ps differential sstl-18 class ii 132 270 330 ps differential hstl-18 class i 135 240 240 ps differential hstl-18 class ii 165 240 285 ps differential hstl-15 class i 220 335 335 ps differential hstl-15 class ii 190 210 375 ps lvds 110 120 125 ps simple rsds 125 125 275 ps mini-lvds 110 120 125 ps notes to ta b l e 5 ? 5 8 : (1) the dcd specification is characterized using the maximum drive strength available for each i/o standard. (2) numbers are applicable for both commercial and industrial devices.
altera corporation 5?71 february 2007 cyclone ii device handbook, volume 1 dc characteristics & timing specifications document revision history table 5?59 shows the revision history for this document. table 5?59. document revision history date & document version changes made summary of changes february 2007 v3.1 added document revision history. added new row in table 5?1 . deleted a sentence from note (1) in table 5?2 . updated table 5?3 . updated table 5?3 . added new note (6) to ta b l e 5 ? 8 . updated note (1) to table 5?12 . updated table 5?13 . updated ?timing specifications? section. updated table 5?45 . added ta b l e 5 ? 4 6 . updated note (2) to table 5?50 . updated ?pll timing specifications? section. updated note (3) to table 5?54 . added v cca minimum and maximum limitations in table 5?1 . updated the maximum v cc rise time for cyclone ii ?a? devices in ta b l e 5 ? 2 . updated r conf information in table 5?3 . changed v i to i i in table 5?3 . updated lvpecl clock inputs in note (6) to table 5?8 . clarified c vref capacitance description in table 5?13 . information on toggle rate derating factors added in table 5?46 . corrected calculation of the period based on a 640 mbps data rate as 1562.5 ps in note (2) to table 5?50 . updated chapter with extended temperature information. clarified v co range of 300-500 mhz usage in note (3) to table 5?54 . december 2005 v2.2 updated pll timing specifications november 2005 v2.1 updated technical content throughout. july 2005 v2.0 updated technical content throughout. november 2004 v1.1 updated the ?differential i/o standards? section. updated table 5?54 . june 2004 v1.0 added document to the cyclone ii device handbook.
5?72 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history
altera corporation 6?1 february 2007 6. reference & ordering information software cyclone ? ii devices are supported by the altera ? quartus ? ii design software, which provides a co mprehensive environment for system-on-a-programmable-chip (sopc) design. the quartus ii software includes hdl and schematic design entry, compilation and logic synthesis, full simulation and adva nced timing anal ysis, signaltap ? ii logic analyzer, and device configuration. see the quartus ii handbook for more information on the quartus ii software features. the free quartus ii web edit ion software, available at www.altera.com , supports microsoft window s xp and windows 2000. the full version of quartus ii software is available thro ugh the altera subscription program. the full version of quartus ii software supports all altera devices, is available for windows xp, windows 2000, sun solaris, and red hat linux operating systems, and includes a free suite of popular ip megacore ? functions for dsp applications and interfacing to external memory devices. quartus ii soft ware and quartus ii web edition software support seamless integration with your favorite third party eda tools. device pin-outs device pin-outs for cyclone ii devices are available on the altera web site ( www.altera.com ). for more information co ntact altera applications. ordering information figure 6?1 describes the ordering codes for cyclone ii devices. for more information on a specific packag e, contact altera applications. cii51006-1.4
6?2 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history figure 6?1. cyclone ii device pa ckaging ordering information document revision history table 6?1 shows the revision history for this document. device type packa g e type 6, 7, or 8 , w ith 6 b eing the fastest nu m b er of pins for a partic u lar package es: t: q: f: u: thin qu ad flat pack (tqfp) plastic qu ad flat pack (pqfp) fineline bga ultra fineline bga ep2c: cyclone ii 5 8 15 20 35 50 70 c: commercial temperat u re (t j = 0 c to 8 5 c) ind u strial temperat u re (t j = -40 c to 100 c) optional suffix family si g nature operatin g temperature speed grade pin count engineering sample 7 ep2c 70 c 324 fes indicates specific de v ice options or shipment method. n : lead-free de v ices i: a fast-on indicates de v ices w ith fast por (po w er on reset) time. table 6?1. document revision history date & document version changes made summary of changes february 2007 v1.5 added document revision history. updated figure 6?1 . added ultra fineline bga detail in ubga package information in figure 6?1 . november 2005 v1.2 updated software introduction. november 2004 v1.1 updated figure 6?1 . june 2004 v1.0 added document to the cyclone ii device handbook.
altera corporation section ii?1 preliminary section ii. clock management this section provides information on the phase-locked loops (plls). cyclone ? ii plls offer general-purp ose clock management with multiplication and phase shifting and also have the ability to drive off chip to control system-level clock networks. this section contains detailed information on the features , the interconnections to the logic array and off chip, and the specifications for cyclone ii plls. this section includes the following chapter: chapter 7, plls in cyclone ii devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the complete handbook.
section ii?2 altera corporation preliminary revision history cyclone ii device handbook, volume 1
altera corporation 7?1 february 2007 7. plls in cyclone ii devices introduction cyclone ? ii devices have up to four ph ase-locked loops (plls) that provide robust clock management and synthesis for device clock management, external system cloc k management, and i/o interfaces. cyclone ii plls are versatile and can be used as a zero delay buffer, a jitter attenuator, a low skew fan out buffer, or a frequency synthesizer. each cyclone ii device has up to four plls, supporting advanced capabilities such as clock switchover and programmable switchover. these plls offer clock mu ltiplication and division, phase shifting, and programmable duty cycle and can be used to minimize clock delay and clock skew, and to reduce or adjust clock-to-out (t co ) and set-up (t su ) times. cyclone ii devices also support a power-down mode where unused clock networks can be turned off. the altera ? quartus ? ii software enables the plls and their features without requiring any external devices. 1 cyclone ii plls have been characterized to operate in the commercial junction temperature range (0 to 85 c), the industrial junction temperatur e range (-40 to 100 c) and the extended temperature range (-40 to 125 c). table 7?1 shows the plls available in each cyclone ii device. table 7?1. cyclone ii device pll availability device pll1 pll2 pll3 pll4 ep2c5 vv ep2c8 vv ep2c15 vvvv ep2c20 vvvv ep2c35 vvvv ep2c50 vvvv ep2c70 vvvv cii51007-3.1
7?2 altera corporation cyclone ii device handbook, volume 1 february 2007 cyclone ii pll hardware overview table 7?2 provides an overview of the cyclone ii pll features. cyclone ii pll hardware overview cyclone ii devices contain up to four plls that are arranged in the four corners of the cyclone ii device as shown in figure 7?1 , which shows a top-level diagram of the cyclone i i device and the pll locations. table 7?2. cyclone ii pll features feature description clock multiplication and division m / ( n post-scale counter) (1) phase shift down to 125-ps increments (2) , (3) programmable duty cycle v number of internal clock outputs up to three per pll (4) number of external clock outputs one per pll (4) locked port can feed logic array v pll clock outputs can feed logic array v manual clock switchover v gated lock v notes to ta b l e 7 ? 2 : (1) m and post-scale counter values range from 1 to 32. n ranges from 1 to 4. (2) the smallest phase shift is determined by the voltage control oscillator (vco) period divided by 8. (3) for degree increments, cyclone ii devi ces can shift output frequencies in increments of at least 45. smaller de gree increments are possible depending on the vco frequency. (4) the cyclone ii pll has three output counte rs that drive the global clock network. one of these output counters (c2) can also drive a dedicated external i/o pin (single ended or differential). this counter output can also drive the external clock output ( pll <#> _out ) and internal global clock network at the same time.
altera corporation 7?3 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices figure 7?1. cyclone ii device pll locations note (1) note to figure 7?1 : (1) this figure shows the pll and clock inputs in the ep2c15 through ep2c70 devices. the ep2c5 and ep2c8 devices only have eight global clocks ( clk[0..3] and clk[4..7] ) and plls 1 and 2. the main purpose of a pll is to sync hronize the phase and frequency of the vco to an input reference clock. there are a number of components that comprise a pll to achi eve this phase alignment. the pll compares the rising edge of the reference input clock to a feedback clock using a phase-freq uency detector (pfd). the pfd produces an up or down signal th at determines whether the vco needs to operate at a higher or lower frequency. the pfd output is applied to the charge pump and loop filter, which produces a control voltage for setting the frequency of the vco. if the pfd transition s the up signal high, then the vco frequency increase s. if the pfd transitions the down signal high, then the vco frequency decreases. clk[0..3] clk[8..11] gclk[0..3] gclk[4..7] gclk[12..15] gclk[8..11] clk[12..15] clk[4..7] pll 1 pll 4 pll 2 pll 3 i/o bank 3 i/o bank 4 i/o bank 8 i/o bank 7 i/o bank 6 i/o bank 5 i/o bank 1 i/o bank 2
7?4 altera corporation cyclone ii device handbook, volume 1 february 2007 cyclone ii pll hardware overview the loop filter converts these up an d down signals to a voltage that is used to bias the vco. if the charge p ump receives a logic high on the up signal, current is driven into the loop filter. if the charge pump receives a logic high on the down signal, curren t is drawn from the loop filter. the loop filter filters out glitches from the charge pump and prevents voltage over-shoot, which minimizes the jitter on the vco. the voltage from the charge pump determines how fast the vco operates. the vco is implemented as an four-stage differential ring oscillator. a divide counter, m , is inserted in the feedback loop to increase the vco frequency above the input re ference frequency, making the vco frequency f vco = m f ref . therefore, the feedback clock, f fb , applied to one input of the pfd, is locked to the input reference clock, f ref (f in / n ), applied to the other input of the pfd. the vco output can feed up to three post-scale counters (c0, c1, and c2). these post-scale counters allow a number of harmonically related frequencies to be produced by the pll. additionally, cyclone ii plls ha ve internal delay elements to compensate for routing on the global clock networks and i/o buffers. these internal delays are fixed and not accessible to the user. figure 7?2 shows a simplified block diagram of the major components of a cyclone ii device pll.
altera corporation 7?5 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices figure 7?2. cyclone ii pll block diagram notes to figure 7?2 : (1) this input can be single-ended or diffe rential. if you are using a differential i/o standard, then the design uses two clock pins. lvds input is supported via the secondary fu nction of the dedicated clock pins. for example, the clk0 pin?s secondary function is lvdsclk1p and the clk1 pin?s secondary function is lvdsclk1n . figure 7?2 shows the possible clock input connections to pll 1. (2) this counter output is shared between a dedicated external clock output ( pll < # > _out ) and the global clock network. (3) if the vco post scale counter = 2, a 300- to 500-mhz internal vco frequency is available. the cyclone ii pll supports up to th ree global clock outputs and one dedicated external clock output. the output frequency to the global clock network or dedicated external clock output is determined by using the following equation: f in is the clock input to the pll and c is the setting on the c0, c1, or c2 counter. the vco frequency is determined in all cases by using the following equation: pfd loop filter lock detect & filter vco charge pump c0 c1 c2 m n global clock global clock global clock to i/o or general routing pll< # >_out post-scale counters vco phase selection selectable at each pll output port clk1 clk3 clk2 (1) clk0 (1) inclk0 inclk1 up down 8 8 8 f vco f fb f in reference input clock f ref = f in / n (2) manual clock switchover select signal k (3) f global/external = f in m n c f vco = f in m n
7?6 altera corporation cyclone ii device handbook, volume 1 february 2007 cyclone ii pll hardware overview the vco frequency is a critical para meter that must be between 300 and 1,000 mhz to ensure proper operatio n of the pll. the quartus ii software automatically sets the vc o frequency within the recommended range based on the clock output and phase-shift requirements in your design. pll reference clock generation in cyclone ii devices, up to four cloc k pins can drive the pll, as shown in figure 7?11 on page 7?26 . the multiplexer output feeds the pll reference clock input. the pll has internal delay elements that compensate for the clock delay from th e input pin to the clock input port of the pll. table 7?3 shows the clock input pin co nnections to the plls in the cyclone ii device. each pll can be fed by one of four si ngle-ended or two differential clock input pins. for example, pll 1 can be fed by clk[3..0] when using a single-ended i/o standard . when your design uses a differential i/o standard, these same clock pins have a secondary function as lvdsclk[2..1]p and lvdsclk[2..1]n pins. when usin g differential clocks, the clk0 pin?s secondary function is lvdsclk1p , the clk1 pin?s secondary function is lvdsclk1n , etc. table 7?3. pll clock input pin connections device pll 1 pll 2 pll 3 pll 4 clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 clk8 clk9 clk10 clk11 clk12 clk13 clk14 clk15 ep2c5 vvvv ep2c8 vvvv ep2c15 vvvvvvvv ep2c20 vvvvvvvv ep2c35 vvvvvvvv ep2c50 vvvvvvvv ep2c70 vvvvvvvv
altera corporation 7?7 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices software overview you can use the altpll megafunction in the quartus ii software to enable cyclone ii plls. figure 7?3 shows the available ports in cyclone ii plls and their sources and destinations. the c0 and c1 counters feed the internal global cl ock networks and the c2 counter can feed the global clock network and a dedicated external clock outp ut pin ( pll < # > _out ) at the same time. figure 7?3. cyclone ii pll signals notes to figure 7?3 : (1) these signals can be assigned to either a single-ended or differential i/o standard. (2) the inclk must be driven by one of two dedicated clock input pins. (3) this counter output can drive both a dedicated external clock output ( pll < # > _out ) and the global clock network. inclk[1..0] (2) pllena areset pfdena clkswitch locked c[1..0] (3) c2 internal clock signal physical pins and internal clock signal signal driven by internal logic physical pins signal driven to internal logic (1)
7?8 altera corporation cyclone ii device handbook, volume 1 february 2007 software overview tables 7?4 and 7?5 describe the cyclone ii pl l input and output ports. table 7?4. pll input signals port description source destination inclk[1..0] primary and secondary clock inputs to the pll. dedicated clock input pins n counter pllena pllena is an active high signal that acts as an enable and reset signal for the pll. it can be used for enabling or disabling each pll. when pllena transitions low, the pll clock output ports are driven to gnd and the pll loses lock. once pllena transitions high again, the lock process begins and the pll re-synchronizes to its input reference clock. the pllena port can be driven by an le output or any general-purpose i/o pin. logic array or input pin pll control signal areset areset is an active high signal that resets all pll counters to their initial values. when this signal is driven high the pll resets its counters, clears the pll outputs and loses lock. once this signal is driven low again, the lock process begins and the pll re-synchronizes to its input reference clock. the areset port can be driven by an le output or any general- purpose i/o pin. logic array or input pin pll control signal pfdena pfdena is an active high signal that enables or disables the up/down output signals from the pfd. when pfdena is driven low, the pfd is disabled, while the vco continues to operate. the pll clock outputs continue to toggle regardless of the input clock, but may experience some long- term drift. because t he output clock frequency does not change for some time, you can use the pfdena port as a shutdown or cleanup function when a reliable input clock is no longer available. the pfdena port can be driven by an le output or any general- purpose i/o pin. logic array or input pin pfd clkswitch clkswitch is an active high switchover signal used to initiate manual clock switchover. logic array or input pin pll control signal
altera corporation 7?9 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices table 7?6 shows a list of i/o standards supported in cyclone ii device plls. table 7?5. pll output signals port description source destination c[2..0] pll clock outputs driving th e internal global clock network or external clock output pin ( pll < # > _out ) pll post-scale counter global clock network or external i/o pin locked gives the status of the pll lock. when the pll is locked, this port drives v cc . when the pll is out of lock, this port drives gnd. the locked port may pulse high and low during the pll lock process. pll lock detect circuit logic array or output pin table 7?6. i/o standards supported for cyclone ii plls (part 1 of 2) i/o standard input output inclk lock pll_out lvttl (3.3, 2.5, and 1.8 v) vvv lvcmos (3.3, 2.5, 1.8, and 1.5 v) vvv 3.3-v pci vvv 3.3-v pci-x (1) vvv lvpecl v lvds vvv 1.5 and 1.8 v differential hstl class i and class ii v v (2) 1.8 and 2.5 v differential sstl class i and class ii v v (2) 1.5-v hstl class i vvv 1.5-v hstl class ii (3) vvv 1.8-v hstl class i vvv 1.8-v hstl class ii (3) vvv sstl-18 class i vvv sstl-18 class ii (3) vvv sstl-25 class i vvv
7?10 altera corporation cyclone ii device handbook, volume 1 february 2007 clock feedback modes clock feedback modes cyclone ii plls support four clock feedback modes: normal mode, zero delay buffer mode, no compensati on mode, and source synchronous mode. cyclone ii plls do not have su pport for external feedback mode. all the supported clock feedback modes allow for multiplication and division, phase shifting, and programmable duty cycle. the phase relationships shown in the waveforms in figures 7?4 through 7?6 are for the default (zero degree) phase shif t setting. changing the phase-shift setting changes the relationships between the output clocks from the pll. normal mode in normal mode, the pll phase-aligns the input reference clock with the clock signal at the ports of the registers in the logic array i/o registers to compensate for the internal global clock network delay. use the altpll megafunction in the quartus ii softwa re to define which internal clock output from the pll (c0, c1, or c2) to compensate for. if an external clock output pin ( pll < # > _out ) is used in this mode, there is a phase shift with respect to the cloc k input pin. similarly, if the internal pll clock outputs are used to drive ge neral-purpose i/o pins, there is be phase shift with respect to the clock input pin. figure 7?4 shows an example waveform of the pll clocks? phase relationship in this mode. sstl-25 class ii vvv rsds/mini-lvds (4) vv notes to ta b l e 7 ? 6 : (1) the pci-x i/o standard is su pported only on side i/o pins. (2) differential sstl and hstl ou tputs are only supported on the pll < # > _out pins. (3) these i/o standards are only suppo rted on top and bottom i/o pins. (4) the rsds and mini-lvds pins ar e only supported on output pins. table 7?6. i/o standards supported for cyclone ii plls (part 2 of 2) i/o standard input output inclk lock pll_out
altera corporation 7?11 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices figure 7?4. phase relationship between cyclone ii pll cloc ks in normal mode note to figure 7?4 : (1) the external clock output can lead or lag the pll clock signals. zero delay buffer mode in zero delay buffer mode, the cloc k signal on the pll external clock output pin ( pll < # > _out ), fed by the c2 counter, is phase-aligned with the pll input clock pin for zero delay. if the c[1..0] ports drive internal clock ports, there is a phase shift with respect to the input clock pin. figure 7?5 shows an example waveform of the pll clocks? phase relationship in this mode. pll inclk pll clock at the register clock port external pll clock outputs (1) phase aligned
7?12 altera corporation cyclone ii device handbook, volume 1 february 2007 clock feedback modes figure 7?5. phase relationship between cy clone ii pll clocks in zero delay buffer mode note to figure 7?5 : (1) the internal clock output(s) can lead or lag the external pll clock output ( pll < # > _out ) signals. 1 altera recommends using the same i/o standard on the input and output clocks when using th e cyclone ii pll in zero delay buffer mode. no compensation mode in no compensation mode, the pll does not compensate for any clock networks, which leads to better jitter performance. because the clock feedback into the pfd does not pass through as much circuitry, both the pll internal clock outputs and extern al clock outputs are phase shifted with respect to the pll clock input. figure 7?6 shows an example waveform of the pll clocks? phas e relationship in this mode. pll reference clock at the inp u t pin pll clock at the register clock port (1) external pll clock o u tp u ts at the o u tp u t pin phase aligned
altera corporation 7?13 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices figure 7?6. phase relationship betw een cyclone ii pll clocks in no compensation mode notes to figure 7?6 : (1) internal clocks fed by the pll are in phase with each other. (2) the external clock outputs can lead or lag the pll internal clocks. source-synchronous mode if data and clock arrive at the same time at the input pins, they are guaranteed to keep the same phase re lationship at the clock and data ports of any ioe input register. figure 7?7 shows an example waveform of the clock and data in this mo de. this mode is recommended for source-synchronous data transfer. data and clock signals at the ioe experience similar buffer delays as long as the same i/o standard is used. pll inclk pll clock at the register clock port (1) external pll clock outputs (2) phase aligned
7?14 altera corporation cyclone ii device handbook, volume 1 february 2007 hardware features figure 7?7. phase relationship bet ween cyclone ii pll clocks in source-synchronous compensation mode 1 set the input pin to the register delay chain within the ioe to zero in the quartus ii software for all data pins clocked by a source-synchronous mode pll. hardware features cyclone ii device plls support a number of features for general-purpose clock management. this section discusses clock multiplication and division implementation , phase-shifting implementation and pll lock circuits. clock multiplication & division cyclone ii device plls provide cloc k synthesis for pll output ports using m /( n post-scale) scaling factors. every pll has one pre-scale divider, n , with a range of 1 to 4 and one multiply counter, m , with a range of 1 to 32. the input clock, f in , is divided by a pre-scale counter, n , to produce the input reference clock, f ref , to the pfd. this input reference clock, f ref , is then multiplied by the m feedback factor. the control loop drives the vco frequency to match f in ( m / n ). the equations for these frequencies are: data pin inclk data at register clock at register f ref = f in n f vco = f ref m = f in n m
altera corporation 7?15 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices each output port has a unique post-scale counter to divide down the high-frequency vco. there are three post-scale counters (c0, c1, and c2), which range from 1 to 32. the follow ing equations show the frequencies for the three post-scale counters: all three output counters can drive the global clock network. the c2 output counter can also drive a dedi cated external i/o pin (single ended or differential). this counter output can drive a dedicated external clock output pin ( pll < # > _out ) and the global clock network at the same time. for multiple pll outputs with differen t frequencies, the vco is set to the least common multiple of the output frequencies that meets the vco frequency specifications. then, the po st-scale counters scale down the vco frequency for each pll clock ou tput port. for example, if clock output frequencies required from one pll are 33 and 66 mhz, the vco is set to 330 mhz (the least common multiple in the vco?s range). programmable duty cycle the programmable duty cycle feature allows you to set the pll clock output duty cycles. the du ty cycle is the ratio of the clock output high and low time to the total clock cycle time, expressed as a percentage of high time. this feature is supported on all three pll post-scale counters, c0, c1, and c2, and when using all clock feedback modes. the duty cycle is set by using a low- and high-time count setting for the post-scale counters. the quartus ii so ftware uses the input frequency and target multiply/divide ratio to sele ct the post-scale counter. the granularity of the duty cycle is determined by the post-scale counter value chosen on a pll clock output and is defined as 50% post-scale counter value. for example, if the post -scale counter value is 3, then the allowable duty cycle precision wo uld be 50% 3 = 16.67%. because the altpll megafunction does not accept non-integer values for the duty cycle values, the allowable duty cycles are 17% 33% 50% and 67%. for example, if the c0 counter is 10, th en steps of 5% are possible for duty cycle choices between 5 to 90%. f c0 = = f in n c0 m f vco c0 f c1 = = f in n c1 m f vco c1 f c2 = = f in n c2 m f vco c2
7?16 altera corporation cyclone ii device handbook, volume 1 february 2007 hardware features phase-shifting implementation cyclone ii devices use fine or coarse phase shifts for clock delays because they are more efficient than dela y elements and are independent of process, voltage, and temperature. phase shift is implemented by using a combination of the vco phase output and the counter starting ti me. the vco phase taps and counter starting time are independent of proc ess, voltage, and temperature. the vco phase taps allow you to phase sh ift the cyclone ii pll output clocks with fine resolution. the counter star ting time allows you to phase shift the cyclone ii pll output cloc ks with coarse resolution. fine-resolution phase shifting is im plemented using any of the eight vco phases for the output counters ( c[2..0] ) or the feedback counter ( m ) reference clock. this provides the fi nest resolution for phase shift. the minimum delay time that may be inserted using this method is defined by the equation: f in is input reference clock frequency. for example, if f in is 100 mhz, n is 1 and m is 8, then f vco is 800 mhz and t is 156.25 ps. this delay time is de fined by the pll operating frequency which is governed by the referenc e clock and the counter settings. the second way to implement phase shifts is by delaying the start of the m and post-scale counters for a pred etermined number of counter clocks. this delay time may be expressed as: where s is the value set for the counte r starting time. the counter starting time is called the initial setting in the pll usage section of the compilation report in the quartus ii software. figure 7?8 shows an example of delay insertion using these two methods. the eight phases from the vco are shown and labeled for reference. for this example, outclk0 is based off the 0 phase from the vco and has the s value for the counter set to 1. it is divided by 4 (two vco clocks for high time and two vco clocks for low time). outclk1 is based off the 135 phase tap from the vco and also has the s value for the counter set to 1. it is also divided by 4. in this case, the two clocks are offset by three t fine =t vco = 1 8 = 1 8 f vco n 8 m f in t coarse = = s ? 1 f vco (s ? 1) n m f in
altera corporation 7?17 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices t fine periods. outclk2 is based off the 0 phas e from the vco but has the s value for the counter set to 3. this creates a delay of two t coarse periods. figure 7?8. cyclone ii pll phase shifting using vco phase output & counter delay time control signals the four control signals in cyclone ii plls ( pllena , areset , pfdena , and locked ) control pll operation. pllena the pll enable signal, pllena , enables and disables the pll. you can either enable/disable a single pll (by connecting pllena port independently) or multiple plls (by connecting pllena ports together). the pllena signal is an acti ve-high signal. when pllena is low, the pll clock output ports are driven by gnd and the pll loses lock. all pll counters, including gated lock counte r return to default state. when pllena transitions high, the pll relock s and resynchronizes to the input clock. in cyclone ii devices, the pllena port can be fed by an le output or any general-purpose i/o pi n. there is no dedicated pllena pin. this increases flexibility since each pll can have its own pllena control circuitry or all plls can share the same pllena circuitry. the pllena signal is optional. when it is not en abled in the quartus ii software, the port is internally tied to v cc . t d0-1 t d0-2 1/8 t vco t vco 0? 90? 135? 180? 225? 270? 315? outclk0 outclk1 outclk2 45?
7?18 altera corporation cyclone ii device handbook, volume 1 february 2007 hardware features areset the pll areset signal is the reset and resynchronization input for each pll. the areset signal should be asserted every time the pll loses lock to guarantee correct phase relati onship between the pll input and output clocks. you should include the areset signal in designs if any of the following conditions are true: manual clock switchover is enabled in the design phase relationships between input and output clocks need to be maintained after a loss of lock condition if the input clock to the pll is n ot toggling or is unstable upon powerup, assert the areset signal after the input clock is toggling, staying within the inpu t jitter specification 1 altera recommends using the areset and locked signals in your designs to control and ob serve the status of your pll. the areset signal is an active high sign al and, when driven high, the pll counters reset, clearing the pll output and causing the pll to lose lock. the vco is also set back to its nominal frequency. the clock outputs from the pll are driven to ground as long as areset is active. when areset transitions low, the pll resynchr onizes to its input clock as the pll relocks. if the target vco frequency is below this nominal frequency, then the pll clock output frequency st arts at a higher value than desired during the lock process. in this ca se, altera recommends monitoring the gated locked signal to ensure the pll is fu lly in lock before enabling the clock outputs from the pll. the cy clone ii device can drive this pll input signal from les or any general-purpose i/o pin. the areset signal is optional. when it is not en abled in the quartus ii software, the port is internally tied to gnd. pfdena the pfdena signal is an active high sign al that controls the pfd output in the pll with a programmable gate. if you disable the pfd by transitioning pfdena low, the vco operates at its last set control voltage and frequency value with some long-term drift to a lower frequency. even though the pll clock outp uts continue to toggle regardless of the input clock, the pll could lose lock. the system continues running when the pll goes out of lock or if the input clock is disabled. by maintaining the current frequency, the system has time to store its current settings before shutting down. if the pfdena signal transitions hi gh, the pll relocks and resynchronizes to the input clock. the pfdena input signal can be driven by any general-purpose i/o pin or fr om les. this signal is optional. when it is not enabled in the quartu s ii software, the port is internally tied to v cc .
altera corporation 7?19 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices locked when the locked port output is a logic high level, this indicates a stable pll clock output in phase with th e pll reference input clock. the locked port may toggle as the pll begi ns tracking the reference clock. the locked port of the pll can feed any general-purpose i/o pin or les. the locked signal is optional, but is us eful in monitoring the pll lock process. the locked output indicates that the pll has locked onto the reference clock. you may need to gate the locked signal for use as a system-control signal. either a gated locked signal or an ungated locked signal from the locked port can drive the logic array or an output pin. cyclone ii plls include a programmable counter that holds the locked signal low for a user-selected number of input cl ock transitions. this allows the pll to lock before transitioning the locked signal high. you can use the quartus ii software to set the 20-bit counter value. the device resets and enables both the counter and the pll simultaneously upon power-up and/or the assertion of the pllenable signal. to ensure correct lock circuit operation, and to ensure that the output clocks have the correct phase relationship with respect to the input clock, altera recommends that the input clock be running before the cyclone ii device is configured. figure 7?9 shows the timing waveform for locked and gated locked signals. figure 7?9. timing waveform for locked & gated locked signals filter counter reaches value count pllena reference clock feedback clock locked gated lock
7?20 altera corporation cyclone ii device handbook, volume 1 february 2007 hardware features manual clock switchover the cyclone ii plls support manual switchover of the reference clock through internal logic. this enable s you to switch between two reference input clocks. use this feature for a du al clock domain application such as in a system that turns on the redund ant clock if the primary clock stops running. figure 7?10 shows how the pll input clock (f in ) is generated from one of four possible clock sources. the first stage multiplexing consists of two dedicated multiplexers that generate two single-ended or two differential clocks from four dedicated clock pins. these clock signals are then multiplexed to generate f in by using another dedicated 2-to-1 multiplexer. the first stage multiplexe rs are controlled by configuration bit settings in the configuration file generated by the quartus ii software, while the second stage multiplexe r is either controlled by the configuration bit settings or lo gic array signal to allow the f in to be controlled dynamically. this allows the implementation of a manual clock switchover circuit where the pll reference clock can be switched during user mode for applications that requires clock redundancy. figure 7?10. cyclone ii pll i nput clock generation notes to figure 7?10 : (1) this select line is set thr ough the configuration file. (2) this select line can either be set thro ugh the configuration file or it can be dynamically set in user mode when using the manual switchover feature. f in inclk1 inclk0 clk[ n + 3] clk[ n + 2] clk[ n + 1] clk[ n ] (1) (1) (2)
altera corporation 7?21 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices pll specifications see the dc & switching characteristics chapter in volume 1 of the cyclone ii devi ce handbook for information on pll timing specifications. clocking cyclone ii devices provide up to 16 dedicated clock pins ( clk[15..0] ) that can drive the global clock networks. the sm aller cyclone ii devices (ep2c5 and ep2c8 devices) support four dedicated clock pins on each side (left and right) capable of dr iving a total of eight global clock networks, while the larger devices (ep2c15 devices and larger) support four clock pins on all fo ur sides of the device. these clock pins can drive a total of 16 global clock networks. table 7?7 shows the number of global clocks available across the cyclone ii family members. global clock network global clocks drive throughout the entire device, feeding all device quadrants. all resources within the device (ioes, logic array blocks (labs), dedicated multiplier blocks, and m4k memory blocks) can use the global clock networks as clock so urces. these clock network resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed by an external pin. internal logic can also drive the global clock networ ks for internally generated global clocks and asynchronous clears, clock enables, or other control signals with high fan-out. table 7?7. number of global clocks available in cyclone ii devices device number of global clocks ep2c5 8 ep2c8 8 ep2c15 16 ep2c20 16 ep2c35 16 ep2c50 16 ep2c70 16
7?22 altera corporation cyclone ii device handbook, volume 1 february 2007 clocking table 7?8 shows the clock sources connectivity to the global clock networks. table 7?8. global clock network connections (part 1 of 3) global clock network clock sources global clock networks all cyclone ii devices ep2c15 through ep2c70 devices only 0123456789101112131415 clk0 / lvdsclk0p vv clk1 / lvdsclk0n vv clk2 / lvdsclk1p vv clk3 / lvdsclk1n vv clk4 / lvdsclk2p vv clk5 / lvdsclk2n vv clk6 / lvdsclk3p vv clk7 / lvdsclk3n vv clk8 / lvdsclk4n vv clk9 / lvdsclk4p vv clk10 / lvdsclk5n vv clk11 / lvdsclk5p vv clk12 / lvdsclk6n vv clk13 / lvdsclk6p vv clk14 / lvdsclk7n vv clk15 / lvdsclk7p vv pll1_c0 vv v pll1_c1 vvv pll1_c2 vv pll2_c0 vv v pll2_c1 vvv pll2_c2 vv pll3_c0 vv v pll3_c1 vvv pll3_c2 vv
altera corporation 7?23 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices pll4_c0 vv v pll4_c1 vvv pll4_c2 vv dpclk0 (1) v dpclk1 (1) v dpclk10 (1) , (2) cdpclk0 or cdpclk7 (3) v dpclk2 (1) , (2) cdpclk1 or cdpclk2 (3) v dpclk7 (1) v dpclk6 (1) v dpclk8 (1) , (2) cdpclk5 or cdpclk6 (3) v dpclk4 (1) , (2) cdpclk4 or cdpclk3 (3) v dpclk8 (1) v dpclk11 (1) v dpclk9 (1) v dpclk10 (1) v dpclk5 (1) v dpclk2 (1) v dpclk4 (1) v table 7?8. global clock network connections (part 2 of 3) global clock network clock sources global clock networks all cyclone ii devices ep2c15 through ep2c70 devices only 0123456789101112131415
7?24 altera corporation cyclone ii device handbook, volume 1 february 2007 clocking if the dedicated clock pins are not us ed to feed the glob al clock networks, they can be used as general-purpose input pins to feed the logic array using the multitrack interconnect. however, if they are used as general-purpose input pins, they do n ot have support for an i/o register and must use le-based registers in place of an i/o register. clock control block every global clock network is driven by a clock control block residing either on the top, bottom, left, or righ t side of the cyclone ii device. the global clock network has been opti mized for minimum clock skew and delay. table 7?9 lists the sources that can feed the clock control block, which in turn feeds the global clock networks. dpclk3 (1) v notes to ta b l e 7 ? 8 : (1) see the cyclone ii architecture chapter in volume 1 of the cyclone ii devi ce handbook for more information on dpclk pins. (2) this pin only applies to ep2c5 and ep2c8 devices. (3) these pins only apply to ep2c15 de vices and larger. only one of the two cdpclk pins can feed the clock control block. the other pin can be used as a regular i/o pin. table 7?8. global clock network connections (part 3 of 3) global clock network clock sources global clock networks all cyclone ii devices ep2c15 through ep2c70 devices only 0123456789101112131415 table 7?9. clock control block inputs (part 1 of 2) input description dedicated clock inputs dedicated cloc k input pins can drive clocks or global signals, such as asynchronous clears, presets, or clock enables onto a given global clock network. dual-purpose clock ( dpclk and cdpclk ) i/o inputs dpclk and cdpclk i/o pins are bidirectional dual function pins that can be used for high fan- out control signals, such as protocol signals, trdy and irdy signals for pci, or dqs for ddr, via the global clock network.
altera corporation 7?25 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices in cyclone ii devices, the dedicated clock input pins, pll counter outputs, dual-purpose cloc k i/o inputs, and internal logic can all feed the clock control block for each global clock network. the output from the clock control block in turn feeds the corresponding global clock network. the clock control blocks are arranged on the device periphery and there are a maximum of 16 clock control blocks available per cyclone ii device. the control block has two functions: dynamic global clock network clock source selection global clock network power-down (dynamic enable and disable) figure 7?11 shows the clock control block. pll outputs the pll counter outputs can drive the global clock network. internal logic the global clock network can also be driven through the logic array routing to enable internal logic (les) to drive a high fan-out, low skew signal path. table 7?9. clock control block inputs (part 2 of 2) input description
7?26 altera corporation cyclone ii device handbook, volume 1 february 2007 clocking figure 7?11. clock control block notes to figure 7?11 : (1) the clkswitch signal can either be set through the configuration file or dynamic ally set when using the manual pll switchover feature. the output of the multiplexer is the input reference clock (f in ) for the pll. (2) the clkselect[1..0] signals are fed by internal logic and can be used to dynamically select the clock source for the global clock network when the device is in user mode. (3) the static clock select signals are se t in the configuration file and cannot be dynamically controlled when the device is in user mode. (4) internal logic can be used to enable or dis able the global clock network in user mode. each pll generates three clock outputs through the c[1..0] and c2 counters. two of these clocks can dr ive the global clock network through the clock control block. global clock network clock source generation there are a total of 8 clock control bl ocks on the smaller cyclone ii devices (ep2c5 and ep2c8 devices) and a tota l of 16 clock control blocks on the larger cyclone ii devices (ep2c15 devices and larger). figure 7?12 shows the cyclone ii clock inputs and th e clock control blocks placement. clkswitch (1) static clock select (3) static clock select (3) internal logic clock control block dpclk or cdpclk clkselect[1..0] (2) clkena (4) inclk1 inclk0 clk[ n + 3] clk[ n + 2] clk[ n + 1] clk[ n ] f in c0 c1 c2 pll global clock enable/ disable (3)
altera corporation 7?27 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices figure 7?12. cyclone ii clock co ntrol blocks placement the inputs to the four clock control bl ocks on each side are chosen from among the following clock sources: four clock input pins three pll counter outputs two dpclk pins and two cdpclk pins from both the left and right sides and four dpclk pins and two cdpclk pins from both the top and bottom four signals from internal logic clk[0..3] clk[8..11] gclk[0..3] gclk[4..7] gclk[12..15] gclk[8..11] clk[12..15] clk[4..7] output from pll output from pl l input to pll output from pll output from pll clock control block clock control block clock control block clock control block pll 1 pll 4 pll 2 pll 3 4 3 4 3 4 3 4 3
7?28 altera corporation cyclone ii device handbook, volume 1 february 2007 clocking from the clock sources listed above, only two clock input pins, two pll clock outputs, one dpclk or cdpclk pin, and one source from internal logic can drive into any given clock control blocks, as shown in figure 7?11 . out of these six in puts to any clock control block, the two clock input pins and two pll outputs can be dynamic selected to feed a global clock network. the clock contro l block supports static selection of the dpclk or cdpclk pin and the signal from internal logic. figure 7?13 shows the simplified version of the four clock control blocks on each side of the cyclone ii device periphery. the cyclone ii devices support up to 16 of these clock contro l blocks and this allows for up to a maximum of 16 global clocks in cyclone ii devices. figure 7?13. clock control blocks on each side of the cyclone ii device note to figure 7?13 : (1) the left and right sides of the device have two dpclk pins, and the top and bottom of the device have four dpclk pins. global clock network power down the cyclone ii global clock network can be disabled (powered down) by both static and dynamic approaches . when a clock network is powered down, all the logic fed by the clock network is in an off-state, thereby reducing the overall power consumption of the device. the global clock networks that are not used are automatically powered down through configuration bit sett ings in the configuration file generated by the quartus ii software. the dynamic clock enable or disabl e feature allows internal logic to synchronously control power up or down on the global cl ock networks in the cyclone ii device. this function is independent of the pll and is applied directly on the clock network, as shown in figure 7?11 . the input 4 gclk clock input pins 4 dpclk internal logic clock control block 3 pll outputs 4 2 or 4 (1) cdpclk 2 four clock control blocks on each side of the device
altera corporation 7?29 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices clock sources and the clkena signals for the global clock network multiplexers can be set through th e quartus ii software using the altclkctrl megafunction. clkena signals in cyclone ii devices, the clkena signals are supported at the clock network level. figure 7?14 shows how the clkena is implemented. this allows you to gate off the clock even when a pll is not being used. upon re-enabling the output clock, the pl l does not need a resynchronization or relock period because the clock is gated off at the clock network level. also, the pll can remain locked independent of the clkena signals since the loop-related counters are not affected. figure 7?14. clkena implementation figure 7?15 shows the waveform example for a clock output enable. clkena is synchronous to the falli ng edge of the clock ( clkin ). this feature is useful for applicatio ns that require a low power or sleep mode. the exact amount of power sa ved when using this feature is pending device characterization. dq clkena clkena_out clk_ou t clkin
7?30 altera corporation cyclone ii device handbook, volume 1 february 2007 board layout figure 7?15. clkena implementation the clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during pll resynchronization. altera recommends using the clkena signals when switching the clock source to the plls or the global clock network. the recommended sequence to be followed is: 1. disable the primary output clock by de-asserting the clkena signal. 2. switch to the secondary clock using the dynamic select signals of the clock control block. 3. allow some clock cycles of the secondary clock to pass before re-asserting the clkena signal. the exact number of clock cycles you need to wait before enabling the secondary clock is design dependent. you can build custom logic to ensure glitch-free transition when switching between different clock sources. board layout the pll circuits in cyclone ii devices contain analog components embedded in a digital device. these analog components have separate power and ground pins to minimize noise generated by the digital components. vcca & gnda each cyclone ii pll uses separate vcc and ground pin pairs for their analog circuitry. the anal og circuit power and ground pin for each pll is called vcca_pll < pll number > and gnda_ pll < pll number >. connect clkin clkena clkout
altera corporation 7?31 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices the vcca power pin to a 1.2-v power supply, even if you do not use the pll. isolate the power connected to vcca from the power to the rest of the cyclone ii device or any other digi tal device on the board. you can use one of three different method s of isolating the vcca pin: use separate vcca power planes use a partitioned vcca island within the vccint plane use thick vcca traces separate vcca power plane a mixed signal system is already partitioned into analog and digital sections, each with its own power pl anes on the board. to isolate the vcca pin using a separate vcca power plane, connect the vcca pin to the analog 1.2-v power plane. partitioned vcca island within the vccint plane fully digital systems do not have a separate analog power plane on the board. since it is expensive to add ne w planes to the board, you can create islands for vcca_pll . figure 7?16 shows an example board layout with an analog power island. the dielectric boundary that creates the island should be 25 mils thick. figure 7?16 shows a partitioned plane within v ccint for vcca. figure 7?16. v ccint plane partitioned for vcca island
7?32 altera corporation cyclone ii device handbook, volume 1 february 2007 board layout thick vcca trace because of board constraints, you may not be able to partition a vcca island. instead, run a thick trace from the power supply to each vcca pin. the traces should be at least 20 mils thick. in each of these three cases, you should filter each vcca pin with a decoupling circuit shown in figure 7?17 . place a ferrite bead that exhibits high impedance at frequencies of 50 mhz or higher and a 10 f tantalum parallel capacitor where the power enters the board. decouple each vcca pin with a 0.1 f and 0.001 f parallel combinat ion of ceramic capacitors located as close as possible to the cyclone ii device. you can connect the gnda pins directly to the same ground plane as the device?s digital ground. figure 7?17. pll power schem atic for cyclone ii plls note to figure 7?17 : (1) applies to plls 1 through 4. 1.2v supply ferrite bead repeat for each pll power & groundset cyclone ii device pll<#>_vcca pll<#>_gnda pll<#>vccd pll<#>_gnd .1 f .001 f gnd gnd vccint 10 f
altera corporation 7?33 february 2007 cyclone ii device handbook, volume 1 plls in cyclone ii devices vccd & gnd the digital power and ground pins are labeled vccd_ pll < pll number > and gnd_pll < pll number >. the vccd pin supplies th e power for the digital circuitry in the pll. connec t these vccd pins to the quietest digital supply on the board. in most systems, this is the digital 1.2-v supply supplied to the device?s v ccint pins. connect the vccd pins to a power supply even if you do not use the pll. when connecting the v ccd pins to v ccint , you do not need any filtering or isolation. you can connect the gnd pins directly to the same ground plane as the device?s digital ground. see figure 7?17 . conclusion cyclone ii device plls provide you with complete control of device clocks and system timing. these plls support clock multiplication/division, phase shift, and programmable duty cycle for your cost-sensitive clock synthesis applications. in addition, the clock ne tworks in the cyclone ii device support dynamic selection of the clock source and also support a power-down mode where clock networks that are not being used can easily be turned off, reducing the overall power consumption of the device.
7?34 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history document revision history table 7?10 shows the revision history for this document. table 7?10. document revision history date & document version changes made summary of changes february 2007 v3.1 added document revision history. updated handpara note in ?introduction? . updated note (3) in table 7?2 . updated figure 7?5 . updated ?control signals? section. updated ?thick vcca trace? section. updated chapter with extended temperature information. updated pllena information in ?control signals? section. corrected capacitor unit from10-f to 10 f. december 2005 v2.2 updated industrial temperature range november 2005 v2.1 updated figure 7?12 . updated figure 7?17 . july 2005 v2.0 updated table 7?6 . updated ?hardware features? section. updated ?areset? section. updated table 7?8 . added ?board layout? section. february 2005 v1.2 updated information concerning signals. added a note to figures 7-9 through 7-13 regarding violating the setup or hold time on address registers. november, 2004 v1.1 updated ?introduction? section. june 2004 v1.0 added document to the cyclone ii device handbook.
altera corporation section iii?1 preliminary section iii. memory this section provides information on embedded memory blocks in cyclone ? ii devices and the supported external memory interfaces. this section includes the following chapters: chapter 8, cyclone ii memory blocks chapter 9, external memory interfaces revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the complete handbook.
section iii?2 altera corporation preliminary revision history cyclone ii device handbook, volume 1
altera corporation 8?1 february 2007 8. cyclone ii memory blocks introduction cyclone ? ii devices feature embedded memory structures to address the on-chip memory needs of fpga designs. the embedded memory structure consists of columns of m4k memory blocks that can be configured to provide various memory functions such as ram, first-in first-out (fifo) buffer s, and rom. m4k memory blocks provide over 1 mbit of ram at up to 250-mhz operation (see table 8?2 on page 8?2 for total ram bits per density). overview the m4k blocks support the following features: over 1 mbit of ram available wi thout reducing available logic 4,096 memory bits per block (4,608 bits per block in cluding parity) variable port configurations true dual-port (one read and one write, two reads, or two writes) operation byte enables for data input masking during writes initialization file to pre-load content of memory in ram and rom modes up to 250-mhz operation table 8?1 summarizes the features supported by the m4k memory. table 8?1. summary of m4k memory features (part 1 of 2) feature m4k blocks maximum performance (1) 250 mhz total ram bits (incl uding parity bits) 4,608 configurations 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 parity bits v byte enable v cii51008-2.3
8?2 altera corporation cyclone ii device handbook, volume 1 february 2007 overview table 8?2 shows the capacity and distribut ion of the m4k memory blocks in each cyclone ii device family member. packed mode v address clock enable v single-port mode v simple dual-port mode v true dual-port mode v embedded shift register mode (2) v rom mode v fifo buffer (2) v simple dual-port mixed width support v true dual-port mixed width support v memory initialization file ( .mif ) v mixed-clock mode v power-up condition outputs cleared register clears output registers only same-port read-during-write new data available at positive clock edge mixed-port read-during-write old data available at positive clock edge notes to ta b l e 8 ? 1 : (1) maximum performance information is prel iminary until device characterization. (2) fifo buffers and embedded shift register s require external logic elements (les) for implementing control logic. table 8?2. number of m4k blocks in cyclone ii devices (part 1 of 2) device m4k blocks total ram bits ep2c5 26 119,808 ep2c8 36 165,888 ep2c15 52 239,616 ep2c20 52 239,616 ep2c35 105 483,840 table 8?1. summary of m4k memory features (part 2 of 2) feature m4k blocks
altera corporation 8?3 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks control signals figure 8?1 shows how the register clocks, clears, and control signals are implemented in the cyclone ii memory block. the clock enable control signal cont rols the clock entering the entire memory block, not just the input and ou tput registers. the signal disables the clock so that the memory block do es not see any clock edges and will not perform any operations. cyclone ii devices do not support asynchronous clear signals to input registers. only output registers support asynchronous clears. there are three ways to reset the registers in the m4k blocks: power up the device, use the aclr signal for output register on ly, or assert the device-wide reset signal using the dev_clrn option. 1 when applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately. ep2c50 129 594,432 ep2c70 250 1,152,000 table 8?2. number of m4k blocks in cyclone ii devices (part 2 of 2) device m4k blocks total ram bits
8?4 altera corporation cyclone ii device handbook, volume 1 february 2007 overview figure 8?1. m4k control signal selection parity bit support error detection using parity check is possible using the parity bit, with additional logic im plemented in les to ensure da ta integrity. parity-size data words can also be used for other purposes such as storing user-specified control bits. f see the using parity to detect memory errors white paper for more information. byte enable support all m4k memory blocks support byte en ables that mask the input data so that only specific bytes of data are written. the unwritten bytes retain the previous written value. the write enable ( wren ) signals, along with the byte enable ( byteena ) signals, control the ram block?s write operations. the default value for the byte enable signals is high (e nabled), in which clock_b clocken_a clock_a clocken_b aclr_b aclr_a dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect renwe_b renwe_a 6 local interconnect local interconnect local interconnect local interconnect byteena_b byteena_a addressstall_b addressstall_a
altera corporation 8?5 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks case writing is controlled only by th e write enable signals. there is no clear port to the byte enable register s. m4k blocks support byte enables when the write port has a data width of 1, 2, 4, 8, 9, 16, 18, 32, or 36 bits. when using data widths of 1, 2, 4, 8, and 9 bits, the byte enable behaves as a redundant write enable because the data width is less than or equal to a single byte. table 8?3 summarizes the byte selection. table 8?4 shows the byte enable port control for true dual-port mode. figure 8?2 shows how the wren and byteena signals control the operations of the ram. when a byte enable bit is de-asserted during a write cycle, the corresponding data byte output appears as a ?don?t care? or unknown value. when a byte enable bit is asserted during a write cycle, the corresponding data byte output is the newly written data. table 8?3. byte enable for cyclone ii m4k blocks note (1) byteena[3..0] affected bytes datain 1 datain 2 datain 4 datain 8 datain 9 datain 16 datain 18 datain 32 datain 36 [0] = 1 [0] [1..0] [3..0] [7..0] [8..0] [7..0] [8..0] [7..0] [8..0] [1] = 1-----[15..8][17..9][15..8][17..9] [2] = 1-------[23..16][26..18] [3] = 1-------[31..24][35..27] note to ta b l e 8 ? 3 : (1) any combination of byte enables is possible. table 8?4. byte enable port control for true dual-port mode byteena [3:0] affected port [1:0] port a (1) [3:2] port b (1) note to ta b l e 8 ? 4 : (1) for any data width up to 18 for each port.
8?6 altera corporation cyclone ii device handbook, volume 1 february 2007 overview figure 8?2. cyclone ii byte enable functional waveform packed mode support cyclone ii m4k memory blocks support packed mode. you can implement two single-port memory bl ocks in a single block under the following conditions: each of the two independent block si zes is less than or equal to half of the m4k block size. the maximum data width for each independent block is 18 bits wide. each of the single-port memory blocks is configured in single-clock mode. f see ?single-port mode? on page 8?9 and ?single-clock mode? on page 8?24 for more information. address clock enable cyclone ii m4k memory blocks support address clock enables, which holds the previous address value unti l needed. when the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. inclock wren address data q (asynch) an xxxx a0 a1 a2 a0 a1 a2 doutn abxx xxcd abcd abff ffcd abcd byteena xx 10 01 11 xxxx xx abcd abcd ffff ffff ffff abff ffcd contents at a0 contents at a1 contents at a2
altera corporation 8?7 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks figure 8?3 shows an address clock enable block diagram. the address register output is fed back to its input via a multiplexer. the multiplexer output is selected by th e address clock enable ( addressstall ) signal. address latching is enabled when the addressstall signal goes high (active high). the output of the addres s register is then continuously fed into the input of the register until the addressstall signal goes low. figure 8?3. cyclone ii address clock enable block diagram the address clock enable is typically used for cache memory applications to improve efficiency during a ca che-miss. the default value for the address clock enable signals is low (disabled). figures 8?4 and 8?5 show the address clock enable waveforms during the read and write cycles, respectively. address[0] address[n] addressstall clock 1 0 address[0] register address[n] register address[n] address[0] 1 0
8?8 altera corporation cyclone ii device handbook, volume 1 february 2007 memory modes figure 8?4. cyclone ii address clock enable during read cycle waveform figure 8?5. cyclone ii address clock enab le during write cycle waveform memory modes cyclone ii m4k memory blocks include input registers that synchronize writes and output registers to pipeli ne data, thereby improving system performance. all m4k memory blocks are fully synchronous, meaning that you must send all inputs through a register, but you can either send outputs through a register (pipel ined) or bypass the register (flow-through). inclock rden rdaddress q (synch) a0 a1 a2 a3 a4 a5 a6 q (asynch) an a0 a4 a5 latched address (inside memory) dout0 dout1 dout1 dout4 dout1 dout4 dout5 addressstall a1 doutn-1 dout1 doutn doutn dout1 dout0 dout1 inclock wren wraddress a0 a1 a2 a3 a4 a5 a6 an a0 a4 a5 latched address (inside memory) addressstall a1 data 00 01 02 03 04 05 06 contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 xx 04 xx 00 03 01 xx 02 xx xx xx 05
altera corporation 8?9 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks 1 m4k memory blocks do not su pport asynchronous memory (unregistered inputs). the m4k memory blocks su pport the following modes: single-port simple dual-port true dual-port (bidirectional dual-port) shift register rom fifo buffers 1 violating the setup or hold time on the memory block address registers could corrupt memory contents. this applies to both read and write operations. single-port mode single-port mode supports non-simult aneous read and write operations. figure 8?6 shows the single-port memory configuration for cyclone ii memory blocks. figure 8?6. single-port mode note (1) note to figure 8?6 : (1) two single-port memory blocks can be implemented in a single m4k block in packed mode. in single-port mode, the outputs are in read-during-write mode, which means that during the write operatio n, data written to the ram flows through to the ram outputs. when th e output registers are bypassed, the new data is available on the rising ed ge of the same clock cycle on which it was written. f see ?read-during- write operation at the same address? on page 8?28 for more information about read-during-write mode. the port width configurations for m4k blocks in single-port mode are as follows: q[ ] outclock outclocken outaclr data[ ] address[ ] wren byteena[ ] addressstall inclock inclocken
8?10 altera corporation cyclone ii device handbook, volume 1 february 2007 memory modes 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 figure 8?7 shows timing waveforms for read and write operations in single-port mode. figure 8?7. cyclone ii single- port timing waveforms note to figure 8?7 : (1) the crosses in the data waveform during read mean ?don?t care.? simple dual-port mode simple dual-port mode supports simult aneous read and write operation. figure 8?8 shows the simple dual-port memory configuration. inclock wren address q (synch) an-1 an a0 a1 a2 a3 a4 a5 a6 q (asynch) din-1 din din4 din5 din6 data (1) din-2 din-1 din dout0 dout1 dout2 dout3 din4 din-1 din dout0 dout1 dout2 dout3 din4 din5
altera corporation 8?11 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks figure 8?8. cyclone ii si mple dual-port mode note (1) note to figure 8?8 : (1) simple dual-port ram supports input and output clock mode in addition to the read and write clock mode shown. cyclone ii memory blocks support mi xed-width configurations, allowing different read and write port widths. tables 8?5 and 8?6 show the mixed-width configurations. in simple dual-port mode, the memory blocks have one write enable and one read enable signal. they do not support a clear port on the write enable and read enable registers. when the read enable is deactivated, the current data is retained at the output ports. if the read enable is activated during a write operation with the sa me address location selected, the simple dual-port ram output is th e old data stored at the memory data[ ] wraddress[ ] wren byteena[ ] wr_addressstall wrclock wrclocken rdaddress[ ] rden q[ ] rd_addressstall rdclock rdclocken rd_aclr simple dual-port memory table 8?5. cyclone ii memory block mixed-widt h configurations (s imple dual-port mode) read port write port 4k 12k 21k 4 512 8 256 16 128 32 512 9 256 18 128 36 4k 1 vvvv v v 2k 2 vvvv v v 1k 4 vvvv v v 512 8 vvvv v v 256 16 vvvv v v 128 32 vvvv v v 512 9 vv v 256 18 vv v 128 36 vv v
8?12 altera corporation cyclone ii device handbook, volume 1 february 2007 memory modes address. see ?read-during- write operation at the same address? on page 8?28 for more information. figure 8?9 shows timing waveforms for read and write operations in simple dual-port mode. figure 8?9. cyclone ii simple d ual-port timing waveforms note to figure 8?9 : (1) the crosses in the data waveform during read mean ?don?t care.? true dual-port mode true dual-port mode supports any co mbination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. figure 8?10 shows cyclone ii true dual-port memory configuration. wrclock wren wraddress q (synch) rdclock an-1 an a0 a1 a2 a3 a4 a5 a6 q (asynch) rden rdaddress bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 dout0 din-1 din din4 din5 din6 data (1)
altera corporation 8?13 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks figure 8?10. cyclone ii true dual-port mode note (1) note to figure 8?10 : (1) true dual-port memory supports input an d output clock mode in addition to the independent clock mode shown. the widest bit configuration of the m4 k blocks in true dual-port mode is 256 16-bit (18-bit with parity). the 128 32-bit (36-bit with parity) conf iguration of the m4k block is unavailable because the number of ou tput drivers is equivalent to the maximum bit width. the maximum width of the true dual-port ram equals half of the total number of output drivers because true dual-port ram has outputs on two ports. table 8?6 lists the possible m4k block mixed-port width configurations. in true dual-port configuration, the ram outputs are in read-during-write mode. this means that during a write operation, data being written to the a or b port of the ram flows through to the a or b table 8?6. cyclone ii memory block mixed- port width configurations (true dual-port) read port write port 4k 12k 21k 4 512 8 256 16 512 9 256 18 4k 1 vvv v v 2k 2 vvv v v 1k 4 vvv v v 512 8 vvv v v 256 16 vvv v v 512 9 vv 256 18 vv data_a[ ] address_a[ ] wren_a byteena_a[ ] addressstall_a clock_a enable_a aclr_a q_a[ ] data_b[ ] address_b[ ] wren_b byteena_b[ ] addressstall_b clock_b enable_b aclr_b q_b[ ]
8?14 altera corporation cyclone ii device handbook, volume 1 february 2007 memory modes outputs, respectively. when the output registers are bypassed, the new data is available on the rising edge of the same clock cycle on which it was written. see ?read-during- write operation at the same address? on page 8?28 for waveforms and information on mixed-port read-during-write mode. potential write contentions must be resolved external to the ram because writing to the same address location at both ports results in unknown data storage at that location. f see the cyclone ii device family data sheet in volume 1 of the cyclone ii device handbook for the maximum synchron ous write cycle time. figure 8?11 shows true dual-port timing waveforms for the write operation at port a and the read operation at port b. figure 8?11. cyclone ii true dual-port timing waveforms note to figure 8?11 : (1) the crosses in the data_a waveform during write indicate ?don?t care.? shift register mode cyclone ii memory blocks can implemen t shift registers for digital signal processing (dsp) applicat ions, such as finite impulse response (fir) filters, pseudo-random number generators, multi-channel filtering, and auto-correlation and cross-correlatio n functions. these and other dsp clk_a wren_a address_a q_a (synch) q_b (synch) clk_b an-1 an a0 a1 a2 a3 a4 a5 a6 q_b (asynch) wren_b address_b bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 dout0 q_a (asynch) din-1 din din4 din5 din6 data_a (1) din-2 din-1 din dout0 dout1 dout2 dout3 din4 din-1 din dout0 dout1 dout2 dout3 din4 din5 dout1 dout2 dout1
altera corporation 8?15 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks applications require local data storage, traditionally implemented with standard flip-flops that quickly exha ust many logic cells for large shift registers. a more efficient alternat ive is to use embedded memory as a shift register block, which saves logic cell and routing resources. the size of a ( wmn ) shift register is determ ined by the input data width ( w ), the length of the taps ( m) , and the number of taps ( n ), and must be less than or equal to the maximum number of memory bits, which is 4,608 bits. in addition, the size of ( wn ) must be less than or equal to the maximum width of the block, which is 36 bits. if a larger shift register is required, the memory blocks can be cascaded. data is written into each address locati on at the falling edge of the clock and read from the address at the rising edge of the clock. the shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. figure 8?12 shows the cyclone ii memory block in the shift register mode. figure 8?12. cyclone ii sh ift register mode configuration wrclock wren wraddress q (synch) rdclock an-1 an a0 a1 a2 a3 a4 a5 a6 q (asynch) rden rdaddress bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 dout0 din-1 din din4 din5 din6 data (1)
8?16 altera corporation cyclone ii device handbook, volume 1 february 2007 clock modes rom mode cyclone ii memory blocks support rom mode. a mif initializes the rom contents of these blocks. th e address lines of the rom are registered. the outputs can be registered or unregistered. the rom read operation is identical to the read operation in the single-port ram configuration. fifo buffer mode a single clock or dual clock fifo buffer may be implemented in the memory blocks. dual clock fifo buffers are useful when transferring data from one clock domain to another clock domain. all fifo memory configurations have synchronous in puts. however, the fifo buffer outputs are always combinational (i.e., not registered). simultaneous read and write from an empty fifo buffer is not supported. f see the single- & dual-clock fifo megafunctions user guide for more information on fifo buffers. clock modes depending on which memory mode is selected, the following clock modes are available: independent input/output read/write single-clock table 8?7 shows these clock modes supported by all memory blocks when configured in each respective memory modes. table 8?7. cyclone ii memory clock modes clocking modes true dual-port mode simple dual-port mode single-port mode independent v input/output vvv read/write v single clock vvv
altera corporation 8?17 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks independent clock mode cyclone ii memory blocks can impl ement independent clock mode for true dual-port memory. in this mode, a separate clock is available for each port (a and b). clock a controls all registers on the port a side, while clock b controls all registers on the port b side. each port also supports independent clock enables for port a and b registers. however, ports do not support asynchronous clear signals for the registers. figure 8?13 shows a memory block in independent clock mode.
8?18 altera corporation cyclone ii device handbook, volume 1 february 2007 clock modes figure 8?13. cyclone ii memory bl ock in independent clock mode note (1) note to figure 8?13 : (1) violating the setup or hold time on the memory blo ck address registers could corr upt memory contents. this applies to both read and write operations. 6 d ena q d ena q d ena q data_a[ ] address_a[ ] memory block 256 16 (2) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out enable_a clock_a d ena q wren_a 6 lab row clocks q_a[ ] 6 data_b[ ] address_b[ ] q_b[ ] ena ab ena d q ena d q ena d q d q d ena q byteena_a[ ] byte enable a byte enable b byteena_b[ ] ena d q write pulse generator write pulse generator wren_b enable_b clock_b addressstall_a address clock enable a address clock addressstall_b enable b
altera corporation 8?19 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks input/output clock mode cyclone ii memory blocks can impl ement the input/output clock mode for true and simple dual-port memory. on each of the two ports, a and b, one clock controls all registers for the data, write enable, and address inputs into the memory block. the oth er clock controls the blocks? data output registers. each memory block port also supports independent clock enables for input and output registers. asynchronous clear signals for the registers are not supported. figures 8?14 through 8?16 show the memory block in input/output clock mode for true dual-port, simple dual-port, and single-port modes, respectively.
8?20 altera corporation cyclone ii device handbook, volume 1 february 2007 clock modes figure 8?14. cyclone ii inpu t/output clock mode in true dual-port mode note (1) note to figure 8?14 : (1) violating the setup or hold time on the memory blo ck address registers could corr upt memory contents. this applies to both read and write operations. 6 d ena q d ena q d ena q data_a[ ] address_a[ ] memory block 256 16 (2) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out inclocken inclock d ena q wren_a 6 lab row clocks q_a[ ] 6 data_b[ ] address_b[ ] q_b[ ] ena ab ena d q ena d q ena d q d q d ena q byteena_a[ ] byte enable a byte enable b byteena_b[ ] ena d q write pulse generator write pulse generator wren_b outclocken outclock addressstall_a address clock enable a address clock addressstall_b enable b
altera corporation 8?21 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks figure 8?15. cyclone ii input/o utput clock mode in simple dual-port mode notes (1) , (2) notes to figure 8?15 : (1) violating the setup or hold time on the memory block a ddress registers could corrupt memory contents. this applies to both read and write operations. (2) see the cyclone ii device family data sheet in volume 1 of the cyclone ii devi ce handbook for more information on the multitrack? interconnect. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] rdaddress[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out outclocken inclocken inclock outclock wren rden 6 lab row clocks to multitrack interconnect (2 ) d ena q byteena[ ] byte enable write pulse generator (1) rd_addressstall wr_addressstall read address clock enable write address clock enable
8?22 altera corporation cyclone ii device handbook, volume 1 february 2007 clock modes figure 8?16. cyclone ii inpu t/output clock mode in single-port mode notes (1) , (2) notes to figure 8?16 : (1) violating the setup or hold time on the memory block a ddress registers could corrupt memory contents. this applies to both read and write operations. (2) see the cyclone ii device family data sheet in volume 1 of the cyclone ii devi ce handbook for more information on the multitrack interconnect. read/write clock mode cyclone ii memory blocks can impl ement read/write clock mode for simple dual-port memory. the write clock controls the blocks? data inputs, write address, and write enable signals. the read clock controls the data output, read address, and read enable signals. the memory blocks support independen t clock enables for each clock for the read- and write-side registers. this mode does not support asynchronous clear signals for the registers. figure 8?17 shows a memory block in read/write clock mode. 6 d ena q d ena q d ena q d ena q data[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in address write enable data out outclocken inclocken inclock outclock wren 6 lab row clocks to multitrack interconnect (2 ) d ena q byteena[ ] byte enable write pulse generator addressstall address clock enable
altera corporation 8?23 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks figure 8?17. cyclone ii read /write clock mode notes (1) , (2) notes to figure 8?17 : (1) violating the setup or hold time on the memory blo ck address registers could corr upt memory contents. this applies to both read and write operations. (2) see the cyclone ii device family data sheet in volume 1 of the cyclone ii device handbook for more information on the multitract interconnect. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] rdaddress[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out rdclocken wrclocken wrclock rdclock wren rden 6 lab row clocks to multitrack interconnect (2 ) d ena q byteena[ ] byte enable write pulse generator (1) rd_addressstall wr_addressstall read address clock enable write address clock enable
8?24 altera corporation cyclone ii device handbook, volume 1 february 2007 clock modes single-clock mode cyclone ii memory blocks support sing le-clock mode for true dual-port, simple dual-port, and single-port memo ry. in this mode, a single clock, together with a clock enable, controls all registers of the memory block. this mode does not support asynchronous clear signals for the registers. figures 8?18 through 8?20 show the memory block in single-clock mode for true dual-port, simple dual-port, and single-port modes, respectively.
altera corporation 8?25 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks figure 8?18. cyclone ii si ngle-clock mode in true dual-port mode note (1) note to figure 8?18 : (1) violating the setup or hold time on the memory blo ck address registers could corr upt memory contents. this applies to both read and write operations. 6 d ena q d ena q d ena q data_a[ ] address_a[ ] memory block 256 16 (2) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out enable clock d ena q wren_a 6 lab row clocks q_a[ ] 6 data_b[ ] address_b[ ] q_b[ ] ena ab ena d q ena d q ena d q d q d ena q byteena_a[ ] byte enable a byte enable b byteena_b[ ] ena d q write pulse generator write pulse generator wren_b a ddressstall_a address clock enable a address clock addressstall_b enable b
8?26 altera corporation cyclone ii device handbook, volume 1 february 2007 clock modes figure 8?19. cyclone ii singl e-clock mode in simple dual-port mode notes (1) , (2) notes to figure 8?19 : (1) violating the setup or hold time on the memory block a ddress registers could corrupt memory contents. this applies to both read and write operations. (2) see the cyclone ii device family data sheet in volume 1 of the cyclone ii devi ce handbook for more information on the multitrack interconnect. 6 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] rdaddress[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out enable clock wren rden 6 lab row clocks to multitrack interconnect (2 ) d ena q byteena[ ] byte enable write pulse generator (1) rd_addressstall wr_addressstall read address clock enable write address clock enable
altera corporation 8?27 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks figure 8?20. cyclone ii si ngle-clock mode in single-port mode notes (1) , (2) notes to figure 8?20 : (1) violating the setup or hold time on the memory blo ck address registers could corr upt memory contents. this applies to both read and write operations. (2) see the cyclone ii device family data sheet in volume 1 of the cyclone ii devi ce handbook for more information on the multitrack interconnect. power-up conditions & memory initialization the cyclone ii memory block outputs always power-up to zero, regardless of whether the output registers are used or bypassed. even if an mif pre-loads the contents of th e memory block, the outputs still power up cleared. for example, if address 0 is pre-initialized to ff , m4k blocks power up with the output at 00 . a subsequent read after power up from address 0 outputs the pre-initialized value of ff . 6 d ena q d ena q d ena q d ena q data[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in address write enable data out enable clock wren 6 lab row clocks to multitrack interconnect (2 ) d ena q byteena[ ] byte enable write pulse generator addressstall address clock enable
8?28 altera corporation cyclone ii device handbook, volume 1 february 2007 read-during- write operation at the same address read-during- write operation at the same address the ?same-port read-during-write mode? and ?mixed-port read-during-write mode? sections describe th e functionality of the various ram configurations when reading from an address during a write operation at that same addres s. there are two read-during-write data flows: same-port and mixed-port. figure 8?21 shows the difference between these flows. figure 8?21. cyclone ii read-d uring-write data flow same-port read-during-write mode for read-during-write operation of a single-port ram or the same port of a true dual-port ram, the new data is available on the rising edge of the same clock cycle on which it was written. figure 8?22 shows a sample functional waveform. when using by te enables in true dual-port ram mode, the outputs for the masked by tes on the same port are unknown (see figure 8?2 on page 8?6 ). the non-masked bytes are read out as shown in figure 8?22 . port a data in port b data in port a data out port b data out mixed-port data flow same-port data flow
altera corporation 8?29 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks figure 8?22. cyclone ii same-port read-during-write functionality note (1) note to figure 8?22 : (1) outputs are not registered. mixed-port read-during-write mode this mode applies to a ram in simple or true dual-port mode, which has one port reading and the other port wr iting to the same address location with the same clock. in this mode, you also have two output choices: old data or don't care. in old data mode, a read-during-write operation to different ports causes the ram outputs to reflect the old data at that address location. in don't care mode, the same operation results in a "don't care" or unknown value on the ram outputs. figure 8?23. cyclone ii mix ed-port read-during-write: old data mode note (1) note to figure 8?23 : (1) outputs are not registered. inclock data wren q a b a old inclock data_a wren_a q_b ab a old wren_b b address q address_a and address_b
8?30 altera corporation cyclone ii device handbook, volume 1 february 2007 conclusion figure 8?24. cyclone ii mix ed-port read-during-write: don?t care mode note (1) note to figure 8?24 : (1) outputs are not registered. mixed-port read-during-write is not supported when two different clocks are used in a dual-port ram. the output value is unknown during a mixed-port read-during-write operation. conclusion the m4k memory structure of cyclon e ii devices provides a flexible memory architecture with high memory bandwidth. it addresses the needs of different memory applications in fpga designs with features such as different memory modes, byte enables, parity bit storage, address clock enables, mixed clock mode, shift register mode, mixed-port width support, and true dual-port mode. inclock data_a wren_a q_b ab unknown wren_b b address q address_a and address_b
altera corporation 8?31 february 2007 cyclone ii device handbook, volume 1 cyclone ii memory blocks document revision history table 8?8 shows the revision history for this document. table 8?8. document revision history date & document version changes made summary of changes february 2007 v2.3 added document revision history. updated ?packed mode support? section. updated ?mixed-port read-during-write mode? section and added new figure 8?24 . in packed mode support, the maximum data width for each of the two memory block is 18 bits wide. added don?t care mode information to mixed-port read-during-write mode section. november 2005 v2.1 updated figures 8?13 through 8?20 . july 2005 v2.0 added clear signals section. february 2005 v1.1 added a note to figures 8-13 through 8-20 regarding violating the setup and hol d time on address registers. june 2004 v1.0 added document to the cyclone ii device handbook.
8?32 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history
altera corporation 9?1 february 2007 9. external memory interfaces introduction improving data bandwidth is an important design consideration when trying to enhance system perfor mance without complicating board design. traditionally, doubling the data bandwidth of a system required either doubling the system frequency or doubling the number of data i/o pins. both methods are undesirable because they complicate the overall system design and increase the numb er of i/o pins. using double data rate (ddr) i/o pins to transmit and receive data doubles the data bandwidth while keeping i/o counts low. the ddr architecture uses both edges of a clock to transmit data , which facilitates data transmission at twice the rate of a single data rate (sdr) architecture using the same clock speed while maintaining the same number of i/o pins. ddr transmission should be used where fast data transmission is required for a broad range of applications such as networking, communications, storage, and im age processing. cyclone ? ii devices support a broad range of external memo ry interfaces, such as sdr sdram, ddr sdram, ddr2 sdram, and qdrii sram. dedicated clock delay control circ uitry allows cyclone ii devices to interface with an external memo ry device at clock speeds up to 167 mhz/333 mbps for ddr and ddr2 sdram devices and 167 mhz/667 mbps for qdrii sram devices. although cyclone ii devices also support sdr sdram, this chapter focuses on the implementations of a double data ra te i/o interface using the hardware features available in cyclone ii devi ces and explains briefly how each memory standard uses the cyclone ii features. the easiest way to interface to external memory devices is by using one of the altera ? external memory ip cores listed below. ddr2 sdram controller megacore ? function ddr sdram controller megacore function qdrii sram controller megacore function opencore ? plus evaluations of these cores are available for free to quartus ? ii web edition software users. in addition, altera software subscription customers now receiv e full licenses to these megacore functions as part of the ip-base suite. cii51009-3.1
9?2 altera corporation cyclone ii device handbook, volume 1 february 2007 external memory interface standards external memory interface standards the following sections describe how to use cyclone ii device external memory interfacing features. ddr & ddr2 sdram ddr sdram is a memory architecture that transmits and receives data at twice the clock speed. these devices transfer data on both the rising and falling edge of the clock si gnal. ddr2 sdram is the second generation memory based on the ddr sdram architecture and is capable of data transfer rates of up to 533 mbps. cyclone ii devices support ddr and ddr2 sdram at up to 333 mbps. interface pins ddr and ddr2 sdram devices use inte rface pins such as data (dq), data strobe (dqs), clock, comman d, and address pins to communicate with the memory controller. data is se nt and captured at twice the system clock rate by transferring data on th e positive and negative edge of the clock. the commands and addresses use only one active (positive) edge of a clock. ddr sdram uses single-ended data strobe dqs, while ddr2 sdram has the option to use differential data strobes dqs and dqs#. cyclone ii devices do not use the optional di fferential data strobes for ddr2 sdram interfaces. you can leave the ddr2 sdram memory dqs# pin unconnected, because only the shifte d dqs signal from the clock delay control circuitry captures data. ddr and ddr2 sdram 16 devices use two dqs pins, and each dqs pin is associated with eight dq pins. however, this is not the same as th e 16/18 mode in cyclone ii devices. you need to configure the cyclone ii devi ces to use two sets of pins in 8 mode. similarly, if your 72 memory module uses nine dqs pins where each dqs pin is associated with eight dq pins, configure the cyclone ii device to use nine sets of dqs/dq groups in 8 mode. connect the memory device?s dq an d dqs pins to the cyclone ii dq and dqs pins, respectively, as listed in the cyclone ii pin tables. ddr and ddr2 sdram also use active-high data mask (dm) pins for writes. dm pins are pre-assigned in pin outs fo r cyclone ii devices, and these are the preferred pins. however, you may conn ect the memory device?s dm pins to any of the cyclone ii i/o pins in th e same bank as the dq pins of the fpga. there is one dm pin per dqs/dq group. if the ddr or ddr2 sdram device supports ecc, the design uses an extra dqs/dq group for the ecc pins.
altera corporation 9?3 february 2007 cyclone ii device handbook, volume 1 external memory interfaces you can use any of the user i/o pins for commands and addresses. because of the symmetrical setup an d hold time for the command and address pins at the memory device, you may need to generate these signals from the negative edge of the system clock. the clocks to the sdram device are called ck and ck#. use any of the user i/o pins via the ddr registers to generate the ck and ck# signals to meet the t dqss requirements of the ddr sdram or ddr2 sdram device. the memory device?s t dqss requires the positive edge of the write dqs signal to be within 25% of the positive edge of the ddr sdram and ddr2 sdram clock input. because of strict skew requirements between ck and ck# signals, use adjacent pins to generate the clock pair. surround the pair with buffer pins tied to v cc and pins tied to ground for better noise immunity from other signals. read & write operation when reading from the memory, ddr and ddr2 sdram devices send the data edge-aligned relative to the data strobe. to properly read the data, the data strobe must be center-aligned relative to the data inside the fpga. cyclone ii devices feature clock delay control circuitry to shift the data strobe to the middle of the data window. figure 9?1 shows an example of how the memory sends out the data and data strobe for a burst-of-two operation.
9?4 altera corporation cyclone ii device handbook, volume 1 february 2007 external memory interface standards figure 9?1. example of a 90 shift on the dqs signal notes (1) , (2) notes to figure 9?1 : (1) rldram ii and qdrii sram memory interfaces do not have preamble and postamble specifications. (2) ddr2 sdram does not support a burst length of two. (3) the phase shift required for your system should be based on your timing analysis and may not be 90. during write operations to a ddr or ddr2 sdram device, the fpga must send the data strobe to the memory device center-aligned relative to the data. cyclone ii devices use a pll to center-align the data strobe by generating a 0 phase-shifted system clock for the write data strobes and a ?90 phase-shifted write clock for th e write data pins for the ddr and ddr2 sdram. figure 9?2 shows an example of the relationship between the data and data strobe during a burst-of-two write. figure 9?2. dq & dqs relationship during a ddr & dd r2 sdram write dqs at fpga pin dq at fpga pin dqs at ioe registers dq at ioe registers 90? degree dq pin to r egister delay dqs pin to r egister delay preamble postamble (3) dqs at fpga pin dq at fpga pin
altera corporation 9?5 february 2007 cyclone ii device handbook, volume 1 external memory interfaces qdrii sram qdrii sram is the second generati on of qdr sram devices. qdrii sram devices, which can transfer four words per clock cycle, fulfill the requirements facing next-generation communications system designers. qdrii sram devices provide concurrent reads and writes, zero latency, increased data throughput, and allow simultaneous access to the same address location. interface pins qdrii sram devices use two separate, unidirectional data ports for read and write operations, enabling four times the data transfer compared to single data rate devices. qdrii sram devices use common control and address lines for read and write operations. figure 9?3 shows the block diagram for qdrii sram burst-of-two architecture. figure 9?3. qdrii sram block diagram for burst-of-two architecture qdrii sram burst-of-two devices samp le the read addres s on the rising edge of the clock and the write addres s on the falling edge of the clock. qdrii sram burst-of-four devices samp le both read and write addresses on the clock?s rising edge. connect the memory device?s q ports (read data) to the cyclone ii dq pins. you ca n use any of the cyclone ii device?s user i/o pins in the top and bottom i/o banks for the d ports (write data), commands, and addresses. for maximum performance, altera recommends connecting the d ports (write data) to the cyclone ii dq pins, because the dq pins are pre-assigned to ensure minimal skew. 256k 18 memory array control logic 256k 18 memory array write port read port q cq, cqn c, cn (optional) rpsn data data 36 36 a bwsn wpsn d 18 18 2 2 18 2 discrete qdrii sram device k, kn v ref
9?6 altera corporation cyclone ii device handbook, volume 1 february 2007 external memory interface standards qdrii sram devices use the following clock signals: input clocks k and k# optional output clocks c and c# echo clocks cq and cqn clocks c#, k#, and cqn are logical co mplements of clocks c, k, and cq, respectively. clocks c, c#, k, and k# are inputs to the qdrii sram, and clocks cq and cqn are outputs from the qdrii sram. cyclone ii devices use single-clock mode for qdrii sram interfacing. the k and k# clocks are used for both read an d write operations, and the c and c# clocks are unused. you can generate c, c#, k, and k# cl ocks using any of the i/o registers via the ddr registers. due to strict skew requirements between k and k# signals, use adjacent pins to generate the clock pair. surround the pair with buffer pins tied to v cc and pins tied to gr ound for better noise immunity from other signals. in cyclone ii devices, another dqs pin implements the cqn pin in the qdrii sram memory interface. thes e pins are denoted by dqs/cq# in the pin table. connect cq and cqn pins to the cyclone ii dqs/cq and dqs/cq# pins of the same dq grou ps, respectively. you must configure the dqs/cq and dqs/cq# as bidirect ional pins. howeve r, because cq and cqn pins are output-only pins from the memory device, the cyclone ii device?s qdrii sram memory interface requires that you ground the dqs/cq and dqs/cq# output enable. to capture data presented by the memory device, connect the shifted cq signal to register c i and input register a i . connect the shifted cqn to input register b i . figure 9?4 shows the cq and cqn connect ions for a qdrii sram read.
altera corporation 9?7 february 2007 cyclone ii device handbook, volume 1 external memory interfaces figure 9?4. cq & cqn connecti on for qdrii sram read read & write operation figure 9?5 shows the data and clock relationships in qdrii sram devices at the memory pins during re ads. qdrii sram devices send data within t co time after each rising edge of the read clock c or c# in multi- clock mode or the input clock k or k# in single clock mode. data is valid until t doh time after each rising edge of the read clock c or c# in multi- clock mode or the input clock k or k# in single clock mode. the cq and cqn clocks are edge-align ed with the read data signal. these clocks accompany the read data for data capture in cyclone ii devices. resynch_clk dataout_h le register le register le register dq le register le register dataout_l input register b i input register a neg_reg_out register c sync_reg_h sync_reg_l d t d t i i clock delay control circuitry dqs/cq# (cqn) dqs/cq (cq)
9?8 altera corporation cyclone ii device handbook, volume 1 february 2007 external memory interface standards figure 9?5. data & clock relations hip during a qdrii sram report notes to figure 9?5 : (1) the timing parameter nomenclature is based on the cypress qdrii sram data sheet for cy7c1313v18. (2) t co is the data clock-to-out time and t doh is the data output hold time between burst. (3) t clz and t chz are bus turn-on and turn-off times, respectively. (4) t cqd is the skew between cqn and data edges. (5) t ccqo and t cqoh are skew measurements between the c or c# clocks (or the k or k# clocks in single-clock mode) and the cq or cqn clocks. when writing to qdrii sram devices, the write clock generates the data while the k clock is 90 shifted from the write clock, creating a center- aligned arrangement. c/k cn/kn q qa qa + 1 qa + 2 qa + 3 cq cqn t co (2) t clz (3) t co (2) t chz (3) t cqd (4) t cqd (4) t cqoh (4) t ccqo (5) t doh (2)
altera corporation 9?9 february 2007 cyclone ii device handbook, volume 1 external memory interfaces cyclone ii ddr memory support overview table 9?1 shows the external memory inte rfaces supported in cyclone ii devices. cyclone ii devices support the data strobe or read clock signal (dqs) used in ddr sdram with the clock de lay control circuitry that can shift the incoming dqs signals to center them within the data window. to achieve ddr operation, the ddr input and output registers are implemented using the internal logic element (le) registers. you should use the altdqs and altdq megafunctions in the quartus ii software to implement the ddr registers used for dqs and dq signals, respectively. table 9?1. external memory support in cyclone ii devices note (1) memory standard i/o standard maximum bus width maximum clock rate supported (mhz) maximum data rate supported (mbps) ddr sdram sstl-2 class i (2) 72 167 333 (1) sstl-2 class ii (2) 72 133 267 (1) ddr2 sdram sstl-18 class i (2) 72 167 333 (1) sstl-18 class ii (3) 72 125 250 (1) qdrii sram (4) 1.8-v hstl class i (2) 36 167 667 (1) 1.8-v hstl class ii (3) 36 100 400 (1) notes to ta b l e 9 ? 1 : (1) the data rate is for designs using the clock delay control circuitry. (2) these i/o standards are supported on al l the i/o banks of the cyclone ii device. (3) these i/o standards are supported only on the i/o banks on the top and bottom of the cyclone ii device. (4) for maximum performance, altera recommends using the 1.8-v hstl i/o standard be cause of high er i/o drive strength. qdrii sram devices also su pport the 1.5-v hstl i/o standard.
9?10 altera corporation cyclone ii device handbook, volume 1 february 2007 ddr memory interface pins ddr memory interface pins cyclone ii devices use data (dq), data strobe (dqs), and clock pins to interface with external memory. figure 9?6 shows the dq and dqs pins in the 8/9 mode. figure 9?6. cyclone ii device dq & dqs groups in 8/9 mode notes (1) , (3) notes to figure 9?6 : (1) each dq group consists of a dqs pin, a dm pin, and up to nine dq pins. (2) for the qdrii memory interface, other dqs pins implem ent the cqn pins. these pins are denoted by dqs/cq# in the pin table. (3) this is an idealized pin layout. for the actu al pin layout, refer to the pin tables in the pcb layout guidelines section of the cyclone ii device handbook, volume 1 . data & data strobe pins cyclone ii data pins for the ddr memo ry interfaces are called dq pins. cyclone ii devices can use either bidirectional data strobes or unidirectional read clocks. depending on the external memory interface, either the memory device?s read data strobes or read clocks feed the dqs pins. in cyclone ii devices, all the i/o banks support ddr and ddr2 sdram and qdrii sram memory at up to 167 mhz. all the i/o banks support dqs signals with the dq bus modes of 8/9 and 16/18. cyclone ii devices can support either bidirectional data strobes or unidirectional read clocks. 1 ddr2 and qdrii interfaces with cl ass ii i/o standard can only be implemented on the top and bottom i/o banks of the cyclone ii device. dq pins dqs pin dm pin dq pins (2)
altera corporation 9?11 february 2007 cyclone ii device handbook, volume 1 external memory interfaces in 8 and 16 modes, one dqs pin drives up to 8 or 16 dq pins, respectively, within the group. in th e 9 and 18 modes, a pair of dqs pins (cq and cq#) drives up to 9 or 18 dq pins within the group to support one or two parity bits and the corresponding data bits. if the parity bits or any data bits are not us ed, the extra dq pins can be used as regular user i/o pins. the 9 and 18 modes are used to support the qdrii memory interface. table 9?2 shows the number of dqs/dq groups supported in each cyclone ii density/package combination. table 9?2. cyclone ii dqs & dq bus mode support note (1) device package number of 8 groups number of 9 groups (5) , (6) number of 16 groups number of 18 groups (5) , (6) ep2c5 144-pin tqfp (2) 3 300 208-pin pqfp 7 (3) 433 256-pin fineline bga 8 (3) 4 (7) 44 (7) ep2c8 144-pin tqfp (2) 3 300 208-pin pqfp 7 (3) 4 (7) 33 256-pin fineline bga ? 8 (3) 4 (7) 44 (7) ep2c15 256-pin fineline bga 8 4 4 4 484-pin fineline bga 16 (4) 8 ( 8 ) 88 ( 8 ) ep2c20 240-pin pqfp 8 4 4 4 256-pin fineline bga 8 4 4 4 484-pin fineline bga 16 (4) 8 ( 8 ) 88 ( 8 ) ep2c35 484-pin fineline bga 16 (4) 8 ( 8 ) 88 ( 8 ) 672-pin fineline bga 20 (4) 8 ( 8 ) 88 ( 8 ) ep2c50 484-pin fineline bga 16 (4) 8 ( 8 ) 88 ( 8 ) 672-pin fineline bga 20 (4) 8 ( 8 ) 88 ( 8 ) ep2c70 672-pin fineline bga 20 (4) 8 ( 8 ) 88 ( 8 ) 896-pin fineline bga 20 (4) 8 ( 8 ) 88 ( 8 ) notes to ta b l e 9 ? 2 : (1) numbers are preliminary. (2) ep2c5 and ep2c8 devices in the 144-pin tqfp package do not have any dq pin groups in i/o bank 1. (3) because of available clock resources, only a total of 6 dq/dqs grou ps can be implemented. (4) because of available clock resources, only a total of 14 dq/dqs groups can be implemented. (5) the 9 dqs/dq groups are also used as 8 dqs/dq groups. the 18 dqs/dq groups are also used as 16 dqs/dq groups. (6) for qdrii implementation, if you connect the d ports (writ e data) to the cyclone ii dq pins, the total available 9 dqs /dq and 18 dqs/dq groups are half of that shown in table 9?2 . (7) because of available clock resources, only a total of 3 dq/dqs grou ps can be implemented. (8) because of available clock resources, only a total of 7 dq/dqs grou ps can be implemented.
9?12 altera corporation cyclone ii device handbook, volume 1 february 2007 ddr memory interface pins the dqs pins are listed in the cyclone ii pin tables as dqs[1..0]t , dqs[1..0]b , dqs[1..0]l , and dqs[1..0]r for the ep2c5 and ep2c8 devices and dqs[5..0]t , dqs[5..0]b , dqs[3..0]l , and dqs[3..0]r for the larger devices. the t denotes pins on the top of the device, the b denotes pins on the bottom of the device, the l denotes pins on the left of the device, and the r denotes pins on the right of the device. the corresponding dq pins are marked as dq[5..0]t[8..0] , where [5..0] indicates which dqs group the pins belong to. in the cyclone ii pinouts, the dq groups with 9 dq pins are also used in the 8 mode with the correspondin g dqs pins, leaving the unused dq pin available as a regular i/o pin. th e dq groups that have 18 dq pins are also used in the 16 mode with the corresponding dqs pins, leaving the two unused dq pins available as regular i/o pins. for example, dq1t[8..0] can be used in the 8 mode, provided it is used with dqs1t . the remaining unused dq pin, dq1t8 , is available as a regular i/o pin. when not used as dq or dqs pins, th ese pins are available as regular i/o pins. table 9?3 shows the number of dqs pins supported in each i/o bank in each cyclone ii device density. the dq pin numbering is based on 8/9 mode. there are up to 8 dqs/dq groups in 8 mode or 4 dq s/dq groups in 9 mode in i/o banks for ep2c5 and ep2c8. for the larger devices, there are up to 20 dqs/dq groups in 8 mode or 8 dq s/dq groups in 9 mode. although there are up to 20 dqs/dq groups in the 8 mode available in the larger cyclone ii devices, but because of the available clock resources in the cyclone ii devices, only 16 dqs/dq groups can be utilized for the external memory interface. there is a total of 16 global clock buses available for routing dqs signals but 2 of them are needed for routing the ?90 write clock and the system clock to the external memory devices. this reduces the global clock reso urces to 14 global clock buses for routing dqs signals. incoming dqs signals are all routed to the clock control block, and are then routed to the global clock bus to clock the ddr le registers. for ep2c5 and ep2c8 de vices, the dqs signals are routed table 9?3. available dqs pins in each i/o bank & each device note (1) device top i/o bank bottom i/o bank left i/o bank right i/o bank ep2c5, ep2c8 dqs[1..0]t dqs[1..0]b dqs[1..0]l dqs[1..0]r ep2c15, ep2c20, ep2c35, ep2c50, ep2c70 dqs[5..0]b dqs[5..0]t dqs[3..0]l dqs[3..0]r note to ta b l e 9 ? 3 : (1) numbers are preliminary.
altera corporation 9?13 february 2007 cyclone ii device handbook, volume 1 external memory interfaces directly to the clock control block. for the larger cyclone ii devices, the corner dqs signals are multiplexed be fore they are routed to the clock control block. when you use the corner dqs pins for ddr implementation, there is a degradatio n in the performance of the memory interface. the clock control block is us ed to select from a number of input clock sources, in this case either pll clock outputs or dqs pins, to drive onto the global clock bus. figure 9?7 shows the corner dqs signal mappings for ep2c15 through ep2c70 devices. figure 9?7. corner dqs signal mapp ing for ep2c15?ep2c70 devices notes to figure 9?7 : (1) there are four control blocks on each side. (2) there are a total of 16 global clocks available. (3) only one of the corner dqs pins in each corner can feed the clock control block at a time. the other dqs pins can be used as general purpose i/o pins. (4) pll resource can be lost if all dqs pins from one side are used at the same time. (5) top/bottom and side io e have different timing. pll 4 (4) pll 3 (4) pll 2 (4) dqs1r dqs2r dqs3r dqs0r dqs0l dqs2l dqs3l dqs1l dqs1t dqs[5..2]t pll 1 (4) dqs0t dqs1b dqs[5..2]b dqs0b clock control block (1) clock control block (1) 4 4 4 4 4 3 4 global clock bus (2) (3) (3) (3) (3) 3 3 3
9?14 altera corporation cyclone ii device handbook, volume 1 february 2007 ddr memory interface pins for example, to implement a 72-bit wide sdram memory interface in cyclone ii devices, use 5 dqs/dq gr oups in the top i/o bank and 4 dqs/dq groups in the bottom i/o bank , or vice-versa. in this case, if dqs0t or dqs1t is used for the fifth dqs signal, the dqs2r or dqs2l pins become regular i/o pins and are unavailable for dqs signals in memory interface. for detailed in formation about the global clock network, refer to the global clock network & phase locked loops section in the cyclone ii architecture chapter of the cyclone ii device handbook . you must configure the dq and dqs pi ns as bidirectional ddr pins on all the i/o banks of the device. use the altdq and altdqs megafunctions to configure the dq and dqs paths, respectively. if you only want to use the dq or dqs pins as inputs, for instance in the qdrii memory interface where dq and dqs are unidirectional read data and read clock, set the output enable of the dq or dqs pins to ground. for further information, please refer to the section ?qdrii sram? on page 9?5 of this handbook. clock, command & address pins you can use any of the user i/o pins on all the i/o banks (that support the external memory?s i/o standard) of the device to generate clocks and command and address signals to the memory device. parity, dm & ecc pins you can use any of the dq pins for th e parity pins in cyclone ii devices. cyclone ii devices support parity in the 8/9 and 16/18 modes. there is one parity bit availa ble per 8 bits of data pins. the data mask (dm) pins are required when writing to ddr sdram and ddr2 sdram devices. a low signal on the dm pin indicates that the write is valid. if the dm signal is high, the memory masks the dq signals. in cyclone ii devices, the dm pins are pre-assigned in the device pin outs, and these are the preferred pins . each group of dqs and dq signals requires a dm pin. similar to the dq output signals, the dm signals are clocked by the ?90 shifted clock. some ddr sdram and ddr2 sdram devices support error correction coding (ecc) or parity. parity bit ch ecking is a way to detect errors, but it has no correction capabilities. e cc can detect and automatically correct errors in data transmis sion. in 72-bit ddr sdram, there are 8 ecc pins on top of the 64 data pins. connect the ddr and ddr2 sdram ecc pins to a cyclone ii device?s dqs/dq group. the memory controller needs extra logic to encode and decode the ecc data.
altera corporation 9?15 february 2007 cyclone ii device handbook, volume 1 external memory interfaces phase lock loop (pll) when using the cyclone ii i/o banks to interface with the ddr memory, at least one pll with two outputs is needed to generate the system clock and the write clock. the system cloc k generates the dqs write signals, commands, and addresses. the write cl ock shifts by ?90 from the system clock and generates the dq signals during writes. clock delay control clock delay control circuit on each dqs pin allows a phase shift that center-aligns the incoming dqs signal s within the data window of their corresponding dq data signals. the phase-shifted dqs signals drive the global clock network. this global dq s signal then clocks the dq signals on internal le registers. the clock delay control circuitry is used during the read operations where the dqs sign als are acting as input clocks or strobes. figure 9?8 illustrates ddr sdram inte rfacing from the i/o pins through the dedicated circuitry to the logic array. figure 9?8. ddr sdram interfacing figure 9?1 on page 9?4 shows an example where the dqs signal is shifted by 90. the dqs signal goes through the 90 shift delay set by the clock delay control circuitry and global clock routing delay from the clock delay control circuitry to the dq le registers. the dq signals only goes through routing delays from the dq pin to the dq le registers. the delay dqs oe v cc pll gnd clk dq oe dataa datab resynchronizing to system clock global clock clock delay control circuitry -90? shifted clk adjacent lab les clock control block le register le register le register le register t en/dis dynamic enable/disable circuitry enout ena_register_mode le register le register le register le register le register le register le register le register le register
9?16 altera corporation cyclone ii device handbook, volume 1 february 2007 ddr memory interface pins from dqs pin to the dq le register does not necessarily match the delay from the dq pin to the dq le register. therefore, you must adjust the clock delay control circuitry to compensate for this difference in delays. dqs postamble for external memory interf aces that use a bidirectional read strobe, such as ddr and ddr2 sdram, the dqs sign al is low before going to or coming from the high-impedance state (see figure 9?1 ). the state where dqs is low just after high-impedance is called the preamble and the state where dqs is low just before it goes to high-impedance is called the postamble. there are preamble and postamble specifications for both read and write operations in ddr and ddr2 sdram. if the cyclone ii device or the ddr/ddr2 sdram device does not drive the dq and dqs pins, the signals go to a high-impedance state. because a pull-up resistor terminates both dq and dqs to v tt (1.25 v for sstl-2 and 0.9 v for sstl-18), the effective voltage on the high-impedance line is either 1.25 v or 0.9 v. according to the jede c jesd8-9 specification for sstl-2 i/o standard and the jesd8-15a spec ification for sstl-18 i/o standard, this is an indeterminate logic level, and the input buffer can interpret this as either a logic high or logic low. if there is any noise on the dqs line, the input buffer may interpret that noise as actual strobe edges. cyclone ii devices have non-dedicate d logic that can be configured to prevent a false edge trigger at the end of the dqs postamble. each cyclone ii dqs signal is connected to po stamble logic that consists of a d flip flop (see figure 9?9 ). this register is clocked by the shifted dqs signal. its input is connected to ground. the controller needs to include extra logic to tell the reset signal to re lease the preset signal on the falling dqs edge at the start of the postambl e. this disables any glitches that happen right after the postamble. this postamble logic is automatically implemented by the altera megaco re ddr/ddr2 sdram controller in the le register as part of the open-source datapath.
altera corporation 9?17 february 2007 cyclone ii device handbook, volume 1 external memory interfaces figure 9?9. cyclone ii dqs post amble circuitry connection figure 9?10 shows the timing waveform for figure 9?9 . when the postamble logic detects the falling dqs edge at the start of postamble, it sends out a signal to disable the capture registers to prevent any accidental latching. dq ena qd prn clrn dq ena dq ena t postamble logic enablen reset global clock network dq[7..0] dqs dqs programmable delay chain circuitry dqs' capture register capture register capture register
9?18 altera corporation cyclone ii device handbook, volume 1 february 2007 ddr memory interface pins figure 9?10. cyclone ii dqs po stamble circuitry c ontrol timing waveform ddr input registers in cyclone ii devices, the ddr input registers are implemented with five internal le registers located in the logic array block (lab) adjacent to the ddr input pin (see figure 9?11 ). the ddr data is fed to the first two registers, input register a i and input register b i . input register b i captures the ddr data present during the rising edge of the clock. input register a i captures the ddr data present during the falling edge of the clock. register c i aligns the data before it is transferred to the resynchronization registers. figure 9?11. ddr input implementation dqs dqs' reset enablen resynch_clk dataout_h le register le register le register dq le register le register dataout_l dqs input register b i input register a i neg_reg_out register c i sync_reg_l sync_reg_h t inverted & delayed dqs clock delay control circuitr y ddr input configuration in cyclone ii
altera corporation 9?19 february 2007 cyclone ii device handbook, volume 1 external memory interfaces registers sync_reg_h and sync_reg_l synchronize the two data streams to the rising edge of the resynchronization clock. figure 9?12 shows examples of functional wavefo rms from a double data rate input implementation. figure 9?12. ddr input fun ctional waveforms the cyclone ii ddr input registers require you to invert the incoming dqs signal to ensure proper data transfer. the altdq megafunction automatically adds the inve rter on the clock port of the dq signals. as shown in figure 9?11 , the inverted dqs signal ?s rising edge clocks register a i , its falling edge clocks register b i , and register c i aligns the data clocked by register b i with register a i on the inverted dqs signal?s rising edge. in a ddr memory read operation, the last data coincides with the falling edge of dqs signal. if you do not invert the dqs pin, you do not get this last data because the register does not latch until the next rising edge of the dqs signal. dqs delay_dqs dq output of input register a i output of input register b i output of register c i resync_clk dataout_h dataout_l q1 q0 q1 q2 q3 q0 q0 q2 q3 q2 q1 q0 q3 q2
9?20 altera corporation cyclone ii device handbook, volume 1 february 2007 ddr memory interface pins figure 9?13 shows waveforms of the circuit shown in figure 9?11 . the first set of waveforms in figure 9?13 shows the edge-aligned relationship between the dq and dqs signals at the cyclone ii device pins. the second set of waveforms in figure 9?13 shows what happens if the shifted dqs signal is not inverted. in this case, the last data, q n , does not get latched into the logic array as dqs goes to tri-state after the read postamble time. the third set of waveforms in figure 9?13 shows a proper read operation with the dqs si gnal inverted after the 90 shift. the last data, q n , does get latched. in this case the outputs of register a i and register c i , which correspond to dataout_h and dataout_l ports, are now switched because of the dqs inversion. register a i , register b i , and register c i refer to the nomenclature in figure 9?11 . figure 9?13. dq captures with noni nverted & inverted shifted dqs dq & dqs signals dq at the pin dqs at the pin shifted dqs signal is not inverted shifted dqs signal is inverted dqs shifted by 90? output of register a i (dataout_h) output of register b i output of register c i (dataout_l) dqs inverted and shifted by 90? output of register a i (dataout_h) output of register b i output of register c i (dataout_i) q n - 1 q n - 2 q n q n - 2 q n - 1 q n - 2 q n - 1 q n q n - 2 q n q n - 3 q n - 1
altera corporation 9?21 february 2007 cyclone ii device handbook, volume 1 external memory interfaces ddr output registers figure 9?14 shows a schematic repres entation of ddr output implemented in a cyclone ii device. the ddr output logic is implemented using les in the lab ad jacent to the output pin. two registers synchronize two serial data streams. the registered outputs are then multiplexed by th e common clock to drive the ddr output pin at two times the data rate. figure 9?14. ddr output implementation for dd r memory interfaces while the clock signal is logic-high , the output from output register a o is driven onto the ddr output pin. while the clock signal is logic-low, the output from output register b o is driven onto the ddr output pin. the ddr output pin can be any available user i/o pin. altera recommends the use of altdq and altdqs megafunctions to impl ement this output logic. this automatically provides the required tight placement and routing constraints on the le regi sters and the output multiplexer. figure 9?15 shows examples of functional waveforms from a ddr output implementation. le register le register datain_h datain_l output register b o output register a o data1 data0 sel dq -90? shifted clk
9?22 altera corporation cyclone ii device handbook, volume 1 february 2007 ddr memory interface pins figure 9?15. ddr output waveforms bidirectional ddr registers figure 9?16 shows a bidirectional ddr in terface constructed using the ddr input and ddr output examples described in the previous two sections. as with the ddr inpu t and ddr output examples, the bidirectional ddr pin can be any available user i/o pin. the registers that implement ddr bidirectional logic are les in the lab adjacent to that pin. the tri-state buffer controls when the device drives data onto the bidirectional ddr pin. outclk datain_h datain_l data1 data0 dq d1 d0 d1 d2 d3 d0 d3 d2 d1 d0 d3 d2 d5 d4 d7 d6 d9 d8 d5 d4 d7 d6 d9 d8 d4 d5 d6 d7 d8 d9
altera corporation 9?23 february 2007 cyclone ii device handbook, volume 1 external memory interfaces figure 9?16. bidirectional ddr implementation for ddr memory interfaces note (1) note to figure 9?16 : (1) you can use the altdq and altdqs megafunctions to generate the dq and dqs signals. figure 9?17 shows example waveforms from a bidirectional ddr implementation. resynch_clk dataout_h le register le register le register dq le register le register dataout_l dqs input register b i input register a i neg_reg_out register c i sync_reg_l sync_reg_h le register le register datain_h datain_l output register b o output register a o outclk data1 data0 sel oe tri le register le register sel tri v cc gnd t clock delay control circuitry
9?24 altera corporation cyclone ii device handbook, volume 1 february 2007 conclusion figure 9?17. ddr bidire ctional waveforms conclusion cyclone ii devices support sdr sd ram, ddr sdram, ddr2 sdram, and qdrii sram external memories . cyclone ii devices feature high- speed interfaces that transfer data between external memory devices at up to 167 mhz/333 mbps for ddr and ddr2 sdram devices and 167 mhz/667 mbps for qdrii sram de vices. the clock delay control circuitry allows you to fine tune the phase shift for the input clocks or strobes to properly align clock edges as needed to capture data. outclk oe datain h datain_l data1 data0 dq d1 d0 d1 d2 d3 d0 d3 d2 d1 d0 d3 d2 dqs output of input register a i output of input register b i output of register c i resync_clk dataout_h dataout_l q1 q0 q1 q2 q3 q0 q0 q2 q3 q2 q1 q0 q3 q2
altera corporation 9?25 february 2007 cyclone ii device handbook, volume 1 external memory interfaces document revision history table 9?4 shows the revision history for this document. table 9?4. document revision history date & document version changes made summary of changes february 2007 v3.1 added document revision history. added handpara note in ?data & data strobe pins? section. updated ?ddr output registers? section. elaboration of ddr2 and qdrii interfaces supported by i/o bank included. november 2005, v2.1 introduction updated table 9?2 . updated figure 9?7 . july 2005, v2.0 updated table 9?2 . november 2004, v1.1 moved the ?external memory interface standards? section to follow the ?introduction? section. updated the ?data & data strobe pins? section. updated figures 9?11 , 9?12 , 9?15 , 9?16 , and 9?17 . june 2004, v1.0 added document to the cyclone ii device handbook.
9?26 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history
altera corporation section iv?1 preliminary section iv. i/o standards this section provides information on cyclone ? ii single-e nded, voltage referenced, and differential i/o standards. this section includes the following chapters: chapter 10, selectable i/o standards in cyclone ii devices chapter 11, high-speed differential interfaces in cyclone ii devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the complete handbook.
section iv?2 altera corporation preliminary revision history cyclone ii device handbook, volume 1
altera corporation 10?1 february 2007 10. selectable i/o standards in cyclone ii devices introduction the proliferation of i/o standards and the need for improved i/o performance have made it critical that low-cost devices have flexible i/o capabilities. selectable i/o capabili ties such as sstl-18, sstl-2, and lvds compatibility allow cyclone ? ii devices to connect to other devices on the same printed circuit board (pcb) that may require different operating and i/o voltages. with thes e aspects of implementation easily manipulated using the altera ? quartus ? ii software, the cyclone ii device family allows you to use low cost fpgas while keeping pace with increasing design complexity. this chapter is a guide to understand ing the input and ou tput capabilities of the cyclone ii devices, including: supported i/o standards cyclone ii i/o banks programmable current drive strength i/o termination pad placement and dc guidelines f for information on hot socketing, refer to the hot socketing & power-on reset chapter in volume 1 of the cyclone ii device handbook . for information on esd specifications, refer to the altera reliability report . supported i/o standards cyclone ii devices support the i/o standards shown in table 10?1 . f see the dc characteristics & timing specifications chapter in volume 1 of the cyclone ii device handbook , for more details on the i/o standards discussed in this section, including target data rates and voltage values for each i/o standard. cii51010-2.3
10?2 altera corporation cyclone ii device handbook, volume 1 february 2007 supported i/o standards f see the external memory interfac es in cyclone ii devices chapter in volume 1 of the cyclone ii device handbook for information on the i/o standards supported for external memory applications. table 10?1. cyclone ii supported i/o standar ds & constraints (part 1 of 2) i/o standard type v ccio level top & bottom i/o pins side i/o pins input output clk, dqs user i/o pins clk, dqs pll_out user i/o pins 3.3-v lvttl and lvcmos single ended 3.3 v/ 2.5 v 3.3 v vvv v v 2.5-v lvttl and lvcmos single ended 3.3 v/ 2.5 v 2.5 v vvv v v 1.8-v lvttl and lvcmos single ended 1.8 v/ 1.5 v 1.8 v vvv v v 1.5-v lvcmos single ended 1.8 v/ 1.5 v 1.5 v vvv v v sstl-2 class i voltage referenced 2.5 v 2.5 v vvv v v sstl-2 class ii voltage referenced 2.5 v 2.5 v vvv v v sstl-18 class i voltage referenced 1.8 v 1.8 v vvv v v sstl-18 class ii voltage referenced 1.8 v 1.8 v vv (1) (1) (1) hstl-18 class i voltage referenced 1.8 v 1.8 v vvv v v hstl-18 class ii voltage referenced 1.8 v 1.8 v vv (1) (1) (1) hstl-15 class i voltage referenced 1.5 v 1.5 v vvv v v hstl-15 class ii voltage referenced 1.5 v 1.5 v vv (1) (1) (1) pci and pci-x (2) single ended 3.3 v 3.3 v vv v differential sstl-2 class i or class ii pseudo differential (3) (4) 2.5 v v 2.5 v (4) v (5) v (5) differential sstl-18 class i or class ii pseudo differential (3) (4) 1.8 v v (6) 1.8 v (4) v (5) v (5)
altera corporation 10?3 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices 3.3-v lvttl (eia/jedec standard jesd8-b) the 3.3-v lvttl i/o standard is a general-purpose, single-ended standard used for 3.3-v applications . the lvttl standard defines the dc interface parameters for digital circuits operating from a 3.0-/3.3-v power supply and driving or being driven by lvttl-compatible devices. the lvttl input standard specifies a wider input voltage range of ?0.3v v i 3.9 v. altera recommends an input voltage range of ?0.5v v i 4.1 v. differential hstl-15 class i or class ii pseudo differential (3) (4) 1.5 v v (6) 1.5 v (4) v (5) v (5) differential hstl-18 class i or class ii pseudo differential (3) (4) 1.8 v v (6) 1.8 v (4) v (5) v (5) lvds differential 2.5 v 2.5 v vvv v v rsds and mini-lvds (7) differential (4) 2.5 v vvv lvpecl ( 8 ) differential 3.3 v/ 2.5 v/ 1.8 v/ 1.5 v (4) vv notes to table 10?1 : (1) these pins support sstl-18 class ii an d 1.8- and 1.5-v hstl class ii inputs. (2) pci-x does not meet the iv curve requirement at the linear region. pci-clamp diode is not available on top and bottom i/o pins. (3) pseudo-differential hstl and sstl outputs use two si ngle-ended outputs with the second output programmed as inverted. pseudo-differential hstl and sstl inputs treat differential in puts as two single-ended hstl and sstl inputs and only decode one of them. (4) this i/o standard is not supported on these i/o pins. (5) this i/o standard is only suppo rted on the dedicated clock pins. (6) pll_out does not support differential sstl-18 class ii and differential 1.8 and 1.5-v hstl class ii. (7) mini-lvds and rsds are only supported on output pins. (8) lvpecl is only supported on clock in puts, not dqs and dual-purpose clock pins. table 10?1. cyclone ii supported i/o standar ds & constraints (part 2 of 2) i/o standard type v ccio level top & bottom i/o pins side i/o pins input output clk, dqs user i/o pins clk, dqs pll_out user i/o pins
10?4 altera corporation cyclone ii device handbook, volume 1 february 2007 supported i/o standards 3.3-v lvcmos (eia/jedec standard jesd8-b) the 3.3-v lvcmos i/o standard is a general-purpose, single-ended standard used for 3.3-v applications. the lvcmos standard defines the dc interface parameters for digital circ uits operating from a 3.0- or 3.3-v power supply and driving or being driven by lvcmos-compatible devices. the lvcmos standard specifies the sa me input voltage requirements as lvttl (? 0.3 v v i 3.9 v). the output buffer drives to the rail to meet the minimum high-level output vo ltage requirements. the 3.3-v i/o standard does not require input reference voltages or board terminations. cyclone ii devices support both input and output levels specified by the 3.3-v lvcmos i/o standard. 3.3-v (pci special interest group [sig] pci local bus specification revision 3.0) the pci local bus specification is used for applications that interface to the pci local bus, which provides a processor-independent data path between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. the conventional pci specification revision 3.0 define s the pci hardware environment including the protocol, electrical, mechanical, and configuration specifications for the pci devices an d expansion boards. this standard requires a 3.3-v v ccio . the 3.3-v pci standard does not require input reference voltages or board terminations. the side (left and right) i/o banks on all cycl one ii devices are fully compliant with the 3.3v pci local bus specification revision 3.0 and meet 32-bit/66 mhz operating frequenc y and timing requirements. table 10?2 lists the specific cyclone ii devices that support 64- and 32-bit pci at 66 mhz. table 10?2. cyclone ii 66-mhz pci support (part 1 of 2) device package -6 & -7 speed grades 64 bits 32 bits ep2c5 144-pin tqfp 208-pin pqfp v 256-pin finelinebga ? v
altera corporation 10?5 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices table 10?3 lists the specific cyclone ii devices that support 64-bit and 32-bit pci at 33 mhz. ep2c8 144-pin tqfp 208-pin pqfp v 256-pin fineline bga v ep2c15 256-pin fineline bga v 484-pin fineline bga vv ep2c20 240-pin pqfp v 256-pin fineline bga v 484-pin fineline bga vv ep2c35 484-pin fineline bga vv 672-pin fineline bga vv ep2c50 484-pin fineline bga vv 672-pin fineline bga vv ep2c70 672-pin fineline bga vv 896-pin fineline bga vv table 10?3. cyclone ii 33-mhz pci support (part 1 of 2) device package -6, -7 & -8 speed grades 64 bits 32 bits ep2c5 144-pin tqfp 208-pin pqfp v 256-pin fineline bga v ep2c8 144-pin tqfp 208-pin pqfp v 256-pin fineline bga v ep2c15 256-pin fineline bga v 484-pin fineline bga vv table 10?2. cyclone ii 66-mhz pci support (part 2 of 2) device package -6 & -7 speed grades 64 bits 32 bits
10?6 altera corporation cyclone ii device handbook, volume 1 february 2007 supported i/o standards 3.3-v pci-x the 3.3-v pci-x i/o standard is formulated under pci-x local bus specification revision 1.0 developed by the pci sig. the pci-x 1.0 standard is used for a pplications that interface to the pci local bus. the standard enables the design of systems and devices that operate at clock speeds up to 133 mhz, or 1 gigabit per second (gbps) for a 64-bit bus. the pci-x 1.0 protoco l enhancements enable devices to operate much more efficiently, providing more usable bandwidth at any clock frequency. by using the pci-x 1.0 standard, devices can be designed to meet pci-x 1.0 requirements an d operate as conventional 33- and 66-mhz pci devices when installed in those systems. this standard requires 3.3-v v ccio . cyclone ii devices are full y compliant with the 3.3-v pci-x specification revision 1.0a and meet the 133 mhz operating frequency and timing requirements. the 3.3-v pci-x standard does not require input reference voltages or board terminations. cyclone ii devices support both input and output levels operation for left and right i/o banks. easy-to-use, low-cost pci express solution pci express is rapidly establishing itself as the successor to pci, providing higher performance, increased flexibility, and scalability for next-generation systems without increasing costs, all while maintaining software compatibility with existing pci applications. now you can easily design high volume, low-cost pci express 1 solutions today featuring: ep2c20 240-pin pqfp v 256-pin fineline bga v 484-pin fineline bga vv ep2c35 484-pin fineline bga vv 672-pin fineline bga vv ep2c50 484-pin fineline bga vv 672-pin fineline bga vv ep2c70 672-pin fineline bga vv 896-pin fineline bga vv table 10?3. cyclone ii 33-mhz pci support (part 2 of 2) device package -6, -7 & -8 speed grades 64 bits 32 bits
altera corporation 10?7 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices cyclone ii fpga (ep2c15 or larger) altera pci express compiler 1 megacore ? function external pci express transceiver/phy 2.5-v lvttl (eia/jedec standard eia/jesd8-5) the 2.5-v i/o standard is used fo r 2.5-v lvttl applications. this standard defines the dc interfac e parameters for high-speed, low- voltage, non-terminated digital circuits driving or being driven by other 2.5-v devices. the 2.5-v standard does not require input reference voltages or board terminations. cyclone ii devices suppo rt input and output levels for 2.5-v lvttl. 2.5-v lvcmos (eia/jedec standard eia/jesd8-5) the 2.5-v i/o standard is used fo r 2.5-v lvcmos applications. this standard defines the dc interfac e parameters for high-speed, low- voltage, non-terminated digital circuits driving or being driven by other 2.5-v parts. the 2.5-v standard does not require input reference voltages or board terminations. cyclone ii devices suppo rt input and output levels for 2.5-v lvcmos. sstl-2 class i & ii (eia/jedec standard jesd8-9a) the sstl-2 i/o standard is a 2.5-v memory bus standard used for applications such as high-speed double data rate (ddr) sdram interfaces. this standard defines the input and output specifications for devices that operate in the sstl-2 lo gic switching range of 0.0 to 2.5 v. this standard improves operations in conditions where a bus must be isolated from large stubs. the sstl-2 standard specifies an input voltage range of ? 0.3 v v i v ccio + 0.3 v. sstl-2 requires a v ref value of 1.25 v and a v tt value of 1.25 v connected to the termination resistors (see figures 10?1 and 10?2 ).
10?8 altera corporation cyclone ii device handbook, volume 1 february 2007 supported i/o standards figure 10?1. sstl-2 class i termination figure 10?2. sstl-2 class ii termination cyclone ii devices support both input and output sstl-2 class i and ii levels. pseudo-differential sstl-2 the differential sstl-2 i/o standard (eia/jedec standard jesd8-9a) is a 2.5-v standard used for applicatio ns such as high-speed ddr sdram clock interfaces. this standard suppo rts differential signals in systems using the sstl-2 standard and supplements the sstl-2 standard for differential clocks. the differential sstl-2 standard specifies an input voltage range of ? 0.3 v v i v ccio + 0.3 v. the differential sstl-2 standard does not require an input reference voltage. see figures 10?3 and 10?4 for details on differential sstl-2 terminations. cyclone ii devices do not support true differential sstl-2 standards. cyclone ii devices support pseudo-differential sstl-2 outputs for pll_out pins and pseudo-differential sstl-2 inputs for clock pins. pseudo-differential inputs require an input reference voltage as opposed to the true differential inputs. see table 10?1 on page 10?2 for information about pseudo-differential sstl. output buffer input buffe r v tt = 1.25 v 50 25 z = 50 v ref = 1.25 v output buffer input buffe r v tt = 1.25 v 50 v tt = 1.25 v 50 25 z = 50 v ref = 1.25 v
altera corporation 10?9 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices figure 10?3. sstl-2 class i di fferential termination figure 10?4. sstl-2 class ii d ifferential termination 1.8-v lvttl (eia/jedec standard eia/jesd8-7) the 1.8-v i/o standard is used fo r 1.8-v lvttl applications. this standard defines the dc interfac e parameters for high-speed, low- voltage, non-terminated digital circuits driving or being driven by other 1.8-v parts. the 1.8-v standard does not require input reference voltages or board terminations. cyclone ii devices suppo rt input and output levels for 1.8-v lvttl. differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 1.25 v v tt = 1.25 v 25 25 differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 1.25 v v tt = 1.25 v 50 50 v tt = 1.25 v v tt = 1.25 v 25 25
10?10 altera corporation cyclone ii device handbook, volume 1 february 2007 supported i/o standards 1.8-v lvcmos (eia/jedec standard eia/jesd8-7) the 1.8-v i/o standard is used fo r 1.8-v lvcmos applications. this standard defines the dc interfac e parameters for high-speed, low- voltage, non-terminated digital circuits driving or being driven by other 1.8-v parts. the 1.8-v standard does not require input reference voltages or board terminations. cyclone ii devices suppo rt input and output levels for 1.8-v lvcmos. sstl-18 class i & ii the 1.8-v sstl-18 standard is fo rmulated under jedec standard, jesd815: stub series terminated logic for 1.8v (sstl-18). the sstl-18 i/o standard is a 1.8- v memory bus standard used for applications such as high-speed ddr 2 sdram interfaces. this standard is similar to sstl-2 and defines input and output specifications for devices that are designed to operate in the sstl-18 logic switching range 0.0 to 1.8 v. sstl-18 requires a 0.9-v v ref and a 0.9-v v tt , with the termination resistors connected to both. there are no class definitions for the sstl-18 standard in the jedec specification. the specification of this i/o standard is based on an environmen t that consists of both series and parallel terminating resistors. alte ra provides solutions to two derived applications in jedec specification an d names them class i and class ii to be consistent with other sstl standards. figures 10?5 and 10?6 show sstl-18 class i and ii termination, respectively. cyclone ii devices support both input and output levels. figure 10?5. 1.8-v sstl class i termination output buffer input buffe r v tt = 0.9 v 50 25 z = 50 v ref = 0.9 v
altera corporation 10?11 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices figure 10?6. 1.8-v sstl class ii termination 1.8-v hstl class i & ii the hstl standard is a technology independent i/o standard developed by jedec to provide voltage scalabilit y. it is used for applications designed to operate in the 0.0- to 1. 8-v hstl logic switching range such as quad data rate (qdr) memory clock interfaces. although jedec specifies a maximum v ccio value of 1.6 v, there are various memory chip vendors with hstl standards that require a v ccio of 1.8 v. cyclone ii devices support interfaces with v ccio of 1.8 v for hstl. figures 10?7 and 10?8 show the nominal v ref and v tt required to track the higher value of v ccio . the value of v ref is selected to provide optimum noise margin in the system . cyclone ii devices support both input and output levels of operation. figure 10?7. 1.8-v hstl class i termination figure 10?8. 1.8-v hstl class ii termination output buffer input buffe r v tt = 0.9 v 50 v tt = 0.9 v 50 25 z = 50 v ref = 0.9 v output buffer input buffe r v tt = 0.9 v 50 z = 50 v ref = 0.9 v output buffer input buffe r v tt = 0.9 v 50 z = 50 v ref = 0.9 v v tt = 0.9 v 50
10?12 altera corporation cyclone ii device handbook, volume 1 february 2007 supported i/o standards pseudo-differential sstl-18 cl ass i & differential sstl-18 class ii the 1.8-v differential sstl-18 stan dard is formulated under jedec standard, jesd8-15: stub series te rminated logic for 1.8v (sstl-18). the differential sstl- 18 i/o standard is a 1. 8-v standard used for applications such as high-speed ddr 2 sdram interfaces. this standard supports differential signals in syst ems using the sstl-18 standard and supplements the sstl-18 standard for differential clocks. see figures 10?9 and 10?10 for details on differential sstl-18 termination. cyclone ii devices do not support true differential sstl-18 standards. cyclone ii devices support pseudo-differential sstl-18 outputs for pll_out pins and pseudo-differential sstl-18 inputs for clock pins. pseudo-differential inputs require an input reference voltage as opposed to the true differential inputs. see table 10?1 on page 10?2 for information about pseudo-differential sstl. figure 10?9. differential sstl- 18 class i termination differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.9 v v tt = 0.9 v 25 25
altera corporation 10?13 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices figure 10?10. differential sstl- 18 class ii termination 1.8-v pseudo-differential hstl class i & ii the 1.8-v differential hstl specification is the same as the 1.8-v single-ended hstl specification. it is used for applications designed to operate in the 0.0 to 1.8-v hstl logic switching range such as qdr memory clock interfaces. cyclone ii devices support both input and output levels. see figures 10?11 and 10?12 for details on 1.8-v differential hstl termination. cyclone ii devices do not support true 1.8-v differential hstl standards. cyclone ii devices support pseudo-differential hstl outputs for pll_out pins and pseudo-differential hstl inputs for clock pins. pseudo-differential inputs require an input reference voltage as opposed to the true differential inputs. see table 10?1 on page 10?2 for information about pseudo-differential hstl. figure 10?11. 1.8-v differential hstl class i termination differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.9 v v tt = 0.9 v 50 50 v tt = 0.9 v v tt = 0.9 v 25 25 differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.9 v v tt = 0.9 v
10?14 altera corporation cyclone ii device handbook, volume 1 february 2007 supported i/o standards figure 10?12. 1.8-v differential hstl class ii termination 1.5-v lvcmos (eia/jedec standard jesd8-11) the 1.5-v i/o standard is used for 1.5-v applications . this standard defines the dc interface paramete rs for high-speed, low-voltage, non-terminated digital circuits driving or being driven by other 1.5-v devices. the 1.5-v standard does not require input reference voltages or board terminations. cyclone ii devices suppo rt input and output levels for 1.5-v lvcmos. 1.5-v hstl class i & ii the 1.5-v hstl standard is for mulated under eia/jedec standard, eia/jesd8-6: a 1.5v output buff er supply voltage based interface standard for digital integrated circuits. the 1.5-v hstl i/o standard is used for applications designed to operate in the 0.0- to 1.5-v hstl logic nomi nal switching range. this standard defines single-ended input and output specifications for all hstl- compliant digital integrated circuits. the 1.5-v hstl i/o standard in cyclone ii devices is compatible with the 1.8-v hstl i/o standard in apex? 20ke, apex 20kc, stratix ? ii, stratix gx, stratix, and in cyclone ii devices themselves beca use the input and output voltage thresholds are compatible. see figures 10?13 and 10?14 . cyclone ii devices support both input and output levels with v ref and v tt . differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.9 v v tt = 0.9 v 50 50 v tt = 0.9 v v tt = 0.9 v
altera corporation 10?15 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices figure 10?13. 1.5-v hstl class i termination figure 10?14. 1.5-v hstl class ii termination 1.5-v pseudo-differential hstl class i & ii the 1.5-v differential hstl standa rd is formulated under eia/jedec standard, eia/jesd8-6: a 1.5v output buffer supply voltage based interface standard for digi tal integrated circuits. the 1.5-v differential hstl specification is the same as the 1.5-v single-ended hstl specification. it is used for applications designed to operate in the 0.0- to 1.5-v hstl logic switching range, such as qdr memory clock interfaces. cyclone ii devices support both input and output levels. see figures 10?15 and 10?16 for details on the 1.5-v differential hstl termination. cyclone ii devices do not support true 1.5-v differential hstl standards. cyclone ii devices support pseudo-differential hstl outputs for pll_out pins and pseudo-differential hstl inputs for clock pins. pseudo-differential inputs require an input reference voltage as opposed to the true differential inputs. see table 10?1 on page 10?2 for information about pseudo-differential hstl. output buffer input buffe r v tt = 0.75 v 50 z = 50 v ref = 0.75 v output buffer input buffe r v tt = 0.75 v 50 v tt = 0.75 v 50 z = 50 v ref = 0.75 v
10?16 altera corporation cyclone ii device handbook, volume 1 february 2007 supported i/o standards figure 10?15. 1.5-v differential hstl class i termination figure 10?16. 1.5-v differential hstl class ii termination lvds, rsds & mini-lvds the lvds standard is formulated under ansi/tia/eia standard, ansi/tia/eia-644: electrical ch aracteristics of low voltage differential signalin g interface circuits. the lvds i/o standard is a differen tial high-speed, low-voltage swing, low-power, general-purpose i/o interface standard. this standard is used in applications requiring high-bandwidth data transfer, backplane drivers, and clock distribution. cyclone ii devices are capable of running at a maximum data rate of 805 mbps for input and 640 mbps for output and still meet the ansi/tia/eia-644 standard. because of the low voltage swing of the lvds i/o standard, the electromagnetic interfer ence (emi) effects are much smaller than complementary metal-oxide semiconductor (cmos), differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.75 v v tt = 0.75 v differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.75 v v tt = 0.75 v 50 50 v tt = 0.75 v v tt = 0.75 v
altera corporation 10?17 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices transistor-to-transistor logic (ttl) , and positive (or pseudo) emitter coupled logic (pecl). this low emi makes lvds ideal for applications with low emi requirements or nois e immunity requirements. the lvds standard does not require an input reference voltage. however, it does require a termination resistor of 90 to 110 between the two signals at the input buffer. cyclone ii devices support true differential lvds inputs and outputs. f lvds outputs on cyclone ii need ex ternal resistor network to work properly. see the high speed differential interf aces in cyclone ii devices chapter in volume 1 of the cyclone ii device handbook for more information. for reduced swing differential signaling (rsds), v od ranges from 100 to 600 mv. for mini-lvds, v od ranges from 300 to 600 mv. the differential termination resistor value ranges from 95 to 105 for both rsds and mini-lvds. cyclone ii devices suppo rt rsds/mini-lvds outputs only. differential lvpecl the low voltage positive (or pseudo) emitter coupled logic (lvpecl) standard is a differential interface standard recommending v ccio of 3.3 v. the lvpecl standard also supports v ccio of 2.5 v, 1.8 v and 1.5 v. the standard is used in applications involving video graphics, telecommunications, data communicati ons, and clock distribution. the high-speed, low-voltage swing lvpecl i/o standard uses a positive power supply and is similar to lvds. however, lvpecl has a larger differential output voltage swing th an lvds. the lvpecl standard does not require an input reference voltage, but it does require an external 100- termination resistor between the two signals at the input buffer. figures 10?17 and 10?18 show two alternate termination schemes for lvpecl. lvpecl input standard is su pported at the clock input pins on cyclone ii devices. lvpecl outp ut standard is not supported. figure 10?17. lvpecl dc coupled termination output buffer input buffer 100 z = 50 z = 50
10?18 altera corporation cyclone ii device handbook, volume 1 february 2007 cyclone ii i/o banks figure 10?18. lvpecl ac coupled termination cyclone ii i/o banks the i/o pins on cyclone ii devices ar e grouped together into i/o banks, and each bank has a separate power bus. this allows you to select the preferred i/o standard for a given bank, enabling tremendous flexibility in the cyclone ii device?s i/o support. ep2c5 and ep2c8 devices support fo ur i/o banks. ep2c15, ep2c20, ep2c35, ep2c50, and ep2c70 device s support eight i/o banks. each device i/o pin is associated with one of these specific, numbered i/o banks (see figures 10?19 and 10?20 ). to accommodate voltage-referenced i/o standards, each cyclone ii i/o bank has separate v ref bus. each bank in ep2c5, ep2c8, ep2c15, ep2c20, ep2c35, an d ep2c50 devices supports two vref pins and each bank in ep2c70 devices supports four vref pins. in the event thes e pins are not used as vref pins, they may be used as regular i/o pins. however, they are expected to have slightly higher pin capacitance than other user i/o pins when used with regular user i/o pins. output buffer input buffe r 100 z = 50 z = 50 v ccio v ccio r2 r2 r1 r1 10 to 100 nf 10 to 100 nf
altera corporation 10?19 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices figure 10?19. ep2c5 & ep2c 8 device i/o banks notes (1) , (2) notes to figure 10?19 : (1) this is a top view of the silicon die. (2) this is a graphic representation only. see the pin li st and the quartus ii software for exact pin locations. regular i/o bank individual power bus regular i/o ban k regular i/o bank regular i/o bank 1 2 3 4
10?20 altera corporation cyclone ii device handbook, volume 1 february 2007 cyclone ii i/o banks figure 10?20. ep2c15, ep2c20, ep2c35, ep2c50 & ep2c70 device i/o banks notes (1) , (2) notes to figure 10?20 : (1) this is a top view of the silicon die. (2) this is a graphic representation only. see the pin li st and the quartus ii software for exact pin locations. regular i/o bank regular i/o bank individual power bus regular i/o bank regular i/o bank regular i/o ban k regular i/o bank regular i/o bank regular i/o bank 4 2 1 87 6 5 3
altera corporation 10?21 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices additionally, each cyclone ii i/o bank has its own vccio pins. any single i/o bank can only support one v ccio setting from among 1.5, 1.8, 2.5 or 3.3 v. although there can only be one v ccio voltage per i/o bank, cyclone ii devices permit additional input signaling capabilities, as shown in table 10?4 . any number of supported single-ended or differential standards can be simultaneously supported in a single i/o bank as long as they use compatible v ccio levels for input and output pins. for example, an i/o bank with a 2.5-v v ccio setting can support 2.5-v lvttl inputs and outputs, 2.5-v lvds-compatible inpu ts and outputs, and 3.3-v lvcmos inputs only. voltage-referenced standards can be supported in an i/o bank using any number of single-ended or differential standards as long as they use the same v ref and a compatible v ccio value. for example, if you choose to implement both sstl-2 and sstl-18 in your cyclone ii device, i/o pins using these standards?becaus e they require different v ref values?must be in different banks from each other. however, the same i/o bank can support sstl-2 and 2.5-v lvcmos with the v ccio set to 2.5 v and the v ref set to 1.25 v. table 10?4. acceptable input levels for lvttl & lvcmos bank v ccio (v) acceptable input levels (v) 3.3 2.5 1.8 1.5 3.3 vv (1) 2.5 vv 1.8 v (2) v (2) vv (1) 1.5 v (2) v (2) vv notes to ta b l e 1 0 ? 4 : (1) because the input level does not drive to the rail, the input buffer does not completely shut off, and the i/o current is slightly higher than the default value. (2) these input values overdrive the inpu t buffer, so the pin leakage current is slightly higher than the default value. to drive inputs higher than v ccio but less than 4.0 v, disable the pci clamping diode and turn on allow voltage overdrive for lvttl/lvcmos input pins in settings > device > device & pin options > pin placement tab. this setting allows input pins with lvttl or lvcmos i/o standards to be placed by the quartus ii software in an i/o bank with a lower v ccio voltage than the voltage specified by the pins.
10?22 altera corporation cyclone ii device handbook, volume 1 february 2007 cyclone ii i/o banks f see ?pad placement & dc guidelines? on page 10?27 for more information. table 10?5 shows i/o standards supported when a pin is used as a regular i/o pin in the i/o banks of cyclone ii devices.
altera corporation 10?23 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices table 10?5. cyclone ii regula r i/o standards support i/o standard i/o banks for ep2c15, ep2c20, ep2c35, ep2c50 & ep2c70 devices i/o banks for ep2c5 & ep2c8 devices 123456781234 lv t t l v vvvvvvvvvvv lv c m o s v vvvvvvvvvvv 2.5 v v vvvvvvvvvvv 1.8 v v vvvvvvvvvvv 1.5 v vvvvvvvvvvvv 3.3-v pci v vvvvv 3.3-v pci-x vv vv v v sstl-2 class i v vvvvvvvvvvv sstl-2 class ii vvvvvvvvvvvv sstl-18 class i v vvvvvvvvvvv sstl-18 class ii (1) (1) v v (1) (1) vv (1) v (1) v 1.8-v hstl class i v vvvvvvvvvvv 1.8-v hstl class ii (1) (1) v v (1) (1) vv (1) v (1) v 1.5-v hstl class i v vvvvvvvvvvv 1.5-v hstl class ii (1) (1) v v (1) (1) vv (1) v (1) v pseudo-differential sstl-2 (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) pseudo-differential sstl-18 (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) 1.8-v pseudo- differential hstl (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) 1.5-v pseudo- differential hstl (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) lv d s v vvvvvvvvvvv rsds and mini-lvds (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) differential lvpecl (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) notes to table 10?5 : (1) these i/o banks support ss tl-18 class ii and 1.8- and 1.5-v hstl class ii inputs. (2) pseudo-differential i/o standards are only supported for clock inputs and dedicated pll_out outputs. see table 10?1 for more information. (3) this i/o standard is only supported for outputs. (4) this i/o standard is only supported for the clock inputs.
10?24 altera corporation cyclone ii device handbook, volume 1 february 2007 programmable current drive strength programmable current drive strength the cyclone ii device i/o standards support various output current drive settings as shown in table 10?6 . these programmable drive- strength settings are a valuable tool in helping decrease the effects of simultaneously switching outputs (sso) in conjunction with reducing system noise. the supported settings en sure that the device driver meets the specifications for i oh and i ol of the corresponding i/o standard. table 10?6. programmable drive strength (part 1 of 2) i/o standard i oh /i ol current strength setting (ma) top & bottom i/o pins side i/o pins lvttl (3.3 v) 4 4 88 12 12 16 16 20 20 24 24 lvcmos (3.3 v) 4 4 88 12 12 16 20 24 lvttl and lvcmos (2.5 v) 4 4 88 12 16 lvttl and lvcmos (1.8 v) 2 2 44 66 88 10 10 12 12 lvcmos (1.5 v) 2 2 44 66 8
altera corporation 10?25 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices these drive-strength settings are programmable on a per-pin basis using the quartus ii software. sstl-2 class i 8 8 12 12 sstl-2 class ii 16 16 20 24 sstl-18 class i 6 6 88 10 10 12 sstl-18 class ii 16 18 hstl-18 class i 8 8 10 10 12 12 hstl-18 class ii 16 n/a 18 20 hstl-15 class i 8 8 10 12 hstl-15 class ii 16 n/a table 10?6. programmable drive strength (part 2 of 2) i/o standard i oh /i ol current strength setting (ma) top & bottom i/o pins side i/o pins
10?26 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o termination i/o termination the majority of the cyclone ii i/o standards are single-ended, non-voltage-referenced i/o standards and, as such, the following i/o standards do not specify a re commended termin ation scheme: 3.3-v lvttl and lvcmos 2.5-v lvttl and lvcmos 1.8-v lvttl and lvcmos 1.5-v lvcmos 3.3-v pci and pci-x voltage-referenced i/o standard termination voltage-referenced i/o standards require both an input reference voltage, v ref , and a termination voltage, v tt . the reference voltage of the receiving device tracks the terminatio n voltage of the transmitting device. f for more information on terminat ion for voltage-referenced i/o standards, see ?supported i/o standards? on page 10?1 . differential i/o standard termination differential i/o standards typically require a termination resistor between the two signals at the receiver. the termination resistor must match the differential load impedance of the bus. cyclone ii devices support differential i/o standards lvds, rsds, and mini-lvds, and differential lvpecl. f for more information on termination for differential i/o standards, see ?supported i/o standards? on page 10?1 .
altera corporation 10?27 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices i/o driver impedance matching (r s ) & series termination (r s ) cyclone ii devices support driver im pedance matching to the impedance of the transmission li ne, typically 25 or 50 . when used with the output drivers, on-chip terminat ion (oct) sets the output driver impedance to 25 or 50 by choosing the driver strength . once matching impedance is selected, driver current can not be changed. table 10?7 provides a list of output standards that support impe dance matching. all i/o banks and i/o pins support impedance matching and series termination. dedicated configuration pins and jtag pins do not support impedance matching or series termination. pad placement & dc guidelines this section provides pad placement guidelines for the programmable i/o standards supported by cyclone ii devices and includes essential information for designing systems using the devices? selectable i/o capabilities. this section also discus ses the dc limitati ons and guidelines. quartus ii software provides user controlled restriction relaxation options for some placement constraint s. when a default restriction is relaxed by a user, the quartus ii fitter generates warnings. f for more information about how quartus ii software checks i/o restrictions, see the i/o assignment planning & analysis chapter in the quartus ii handbook . table 10?7. selectable i/o drivers with impedance matching & series termination i/o standard target r s ( ) 3.3-v lvttl/cmos 25 (1) 2.5-v lvttl/cmos 50 (1) 1.8-v lvttl/cmos 50 (1) sstl-2 class i 50 (1) sstl-18 class i 50 (1) note to table 10?7 : (1) these rs values are nominal values. actual impedance vari es across process, voltage, and temperature conditions . tolerance is specified in the dc characteristics & timing specifications chapter of the cyclone ii handbook, volume 1 .
10?28 altera corporation cyclone ii device handbook, volume 1 february 2007 pad placement & dc guidelines differential pad placement guidelines to maintain an acceptable noise level on the v ccio supply, there are restrictions on placement of sing le-ended i/o pads in relation to differential pads in the same i/o bank. use the following guidelines for placing single-ended pads with respect to differential pads and for differential output pads placement in cyclone ii devices. for the lvds i/o standard: single-ended inputs can be no clos er than four pads away from an lvds i/o pad. single-ended outputs can be no clos er than five pads away from an lvds i/o pad. maximum of four 155-mhz (or greate r) lvds output channels per vccio and ground pair. maximum of three 311-mhz (or greater) lvds output channels per vccio and ground pair. the quartus ii software only checks the first two cases. for the rsds and mini-lvds i/o standards: single-ended inputs can be no clos er than four pads away from an rsds and mini-lvds output pad. single-ended outputs can be no clos er than five pads away from an rsds and mini-lvds output pad. maximum of three 85-mhz (or greater) rsds and mini-lvds output channels per vccio and ground pair. the quartus ii software only checks the first two cases. for the lvpecl i/o standard: single-ended inputs can be no clos er than four pads away from an lvpecl input pad. single-ended outputs can be no clos er than five pads away from an lvpecl input pad. v ref pad placement guidelines to maintain an acceptable noise level on the v ccio supply and to prevent output switching noise from shifting the v ref rail, there are restrictions on the placement of single-ended volt age referenced i/os with respect to v ref pads and vccio and ground pairs. use the following guidelines for placing single-ended pads in cyclone ii devices.
altera corporation 10?29 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices the quartus ii software automatically does all the calculations in this section. input pads each v ref pad supports up to 15 input pa ds on each side of the v ref pad for fineline bga devices. each v ref pad supports up to 10 input pads on each side of the v ref pad for quad flat pack (qfp) devices. this is irrespective of vccio and ground pairs, and is guaranteed by the cyclone ii architecture. output pads when a voltage referenced input or bidirectional pad does not exist in a bank, there is no limit to the number of output pads that can be implemented in that bank. when a vo ltage referenced input exists, each vccio and ground pair supports 9 output pins for fineline bga packages (not more than 9 output pi ns per 12 consecutive row i/o pins) or 5 output pins for qfp packages (not more than 5 output pins per 12 consecutive row i/o pins or 8 co nsecutive column i/o pins). any non-sstl and non-hstl output can be no closer than two pads away from a v ref pad. altera recommends that any sstl or hstl output, except for pintable defined dq and dqs outputs, to be no closer than two pads away from a v ref pad to maintain acceptable noise levels. 1 quartus ii software will not check for the sstl and hstl output pads placement rule. f see ?ddr & qdr pads? on page 10?32 for details about guidelines for dq and dqs pads placement. bidirectional pads bidirectional pads must satisfy input and output guidelines simultaneously. f see ?ddr & qdr pads? on page 10?32 for details about guidelines for dq and dqs pads placement. if the bidirectional pads are all contro lled by the same output enable (oe) and there are no other outputs or volt age referenced inpu ts in the bank, then there is no case where there is a voltage referenced input is active at the same time as an ou tput. therefore, the output limitation does not apply. however, since the bidirectional pads are linked to the same oe, all the bidirectional pads act as inputs at the same time. therefore, the
10?30 altera corporation cyclone ii device handbook, volume 1 february 2007 pad placement & dc guidelines input limitation of 30 input pads (15 on each side of the v ref pad) for fineline bga packages and 20 inpu t pads (10 on each side of the v ref pad) for qfp packages applies. if the bidirectional pads are all controlled by different oes, and there are no other outputs or voltage referenced inputs in the bank, then there may be a case where one group of bidirection al pads is acting as inputs while another group is acting as outputs. in such cases, apply the formulas shown in table 10?8 . consider a fineline bga package with four bidirectional pads controlled by the first oe, four bidirectional pa ds controlled by the second oe, and two bidirectional pads controlled by the third oe. if the first and second oes are active and the third oe is inac tive, there are 10 bidirectional pads, but it is safely allowable because th ere would be 8 or fewer outputs per vccio / gnd pair. when at least one additional volt age referenced input and no other outputs exist in the same v ref bank, the bidirectional pad limitation applies in addition to the input and ou tput limitations. see the following equations: total number of bidirectional pads + total number of input pads 30 (15 on each side of your v ref pad) for fineline bga packages total number of bidirectional pads + total number of input pads 20 (10 on each side of your v ref pad) for qfp packages table 10?8. input-only bidirecti onal pad limitation formulas package type formula fineline bga (total number of bidirectional pads) ? (total number of pads from the smallest group of pads controlled by an oe) 9 (per vccio and ground pair) qfp (total number of bidirectional pads) ? (total number of pads from the smallest group of pads controlled by an oe) 5 (per vccio and ground pair).
altera corporation 10?31 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices after applying the equation above, apply one of the equations in table 10?9 , depending on the package type. when at least one additional output exists but no voltage referenced inputs exist, apply the appropriate formula from table 10?10 . when additional voltage referenced in puts and other outputs exist in the same v ref bank, the bidirectional pa d limitation must again simultaneously adhere to the input an d output limitations. as such, the following rules apply: total number of bidirectional pads + total number of input pads 30 (15 on each side of your v ref pad) for fineline bga packages total number of bidirectional pads + total number of input pads 20 (10 on each side of your v ref pad) for qfp packages table 10?9. bidirectional pad limitation formulas (where v ref inputs exist) package type formula fineline bga (total number of bidirectional pads) 9 (per vccio and ground pair) qfp (total number of bidirectional pads) 5 (per vccio and ground pair) table 10?10. bidirectional pad limitation formulas (where v ref outputs exist) package type formula fineline bga (total number of bidire ctional pads) + (total number of additional output pads) ? (total number of pads from the smallest group of pads controlled by an oe) 9 (per vccio and ground pair) qfp (total number of bidirecti onal pads) + (total number of additional output pads) ? (total number of pads from the smallest group of pads controlled by an oe) 5 (per vccio and ground pair)
10?32 altera corporation cyclone ii device handbook, volume 1 february 2007 pad placement & dc guidelines after applying the equation above, apply one of the equations in table 10?11 , depending on the package type. each i/o bank can only be set to a single v ccio voltage level and a single v ref voltage level at a given time. pins of different i/o standards can share the bank if they have compatible v ccio values (see table 10?4 for more details) and compatible v ref voltage levels. ddr & qdr pads for dedicated dq and dqs pads on a ddr interface, dq pads have to be on the same power bank as dqs pads. with the ddr and ddr2 memory interfaces, a vccio and ground pair can have a maximum of five dq pads. for a qdr interface, d is the qdr outp ut and q is the qdr input. d pads and q pads have to be on the same power bank as cq. with the qdr and qdrii memory interfaces, a vccio and ground pair can have a maximum of five d and q pads. by default, the quartus ii software assigns d and q pads as regular i/o pins. if you do not specify the functi on of a d or q pad in the quartus ii software, the software sets them as regular i/o pins. if this occurs, cyclone ii qdr and qdrii perf ormance is not guaranteed. dc guidelines there is a current limit of 240 ma pe r eight consecutive output top and bottom pins per power pair, as shown by the following equation: pin+7 i pin < 240ma per power pair pin there is a current limit of 240 ma per 12 consecutive output side (left and right) pins per power pair, as shown by the following equation: table 10?11. bidirectional pad li mitation formulas (multiple v ref inputs & outputs) package type formula fineline bga (total number of bidire ctional pads) + (total number of output pads) 9 (per vccio / gnd pair) qfp total number of bidirectional pads + total number of output pads 5 (per vccio / gnd pair)
altera corporation 10?33 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices pin+11 i pin < 240ma per power pair pin in all cases listed above, the quartus ii software generates an error message for illegally placed pads. table 10?12 shows the i/o standard dc current specification. table 10?12. cyclone ii i/o standard dc current specification (preliminary) (part 1 of 2) i/o standard i pin (ma) top & bottom banks side banks lv t t l (1) (1) lv c m o s (1) (1) 2.5 v (1) (1) 1.8 v (1) (1) 1.5 v (1) (1) 3.3-v pci not supported 1.5 3.3-v pci-x not supported 1.5 sstl-2 class i 12 (2) 12 (2) sstl-2 class ii 24 (2) 20 (2) sstl-18 class i 12 (2) 12 (2) sstl-18 class ii 8 (2) not supported 1.8-v hstl class i 12 (2) 12 (2) 1.8-v hstl class ii 20 (2) not supported 1.5-v hstl class i 12 (2) 10 (2) 1.5-v hstl class ii 18 (2) not supported differential sstl-2 class i (3) 8.1 (4) differential sstl-2 class ii (3) 16.4 (4) differential sstl-18 class i (3) 6.7 (4) differential sstl-18 class ii (3) 13.4 (4) 1.8-v differential hstl class i (3) 8 (4) 1.8-v differential hstl class ii (3) 16 (4) 1.5-v differential hstl class i (3) 8 (4)
10?34 altera corporation cyclone ii device handbook, volume 1 february 2007 5.0-v device compatibility table 10?12 only shows the limit on the static power consumed by an i/o standard. the amount of total power used at any moment could be much higher, and is based on the switching activities. 5.0-v device compatibility a cyclone ii device may not correctly interoperate with a 5.0-v device if the output of the cyclone ii device is connected directly to the input of the 5.0-v device. if v out of the cyclone ii device is greater than v ccio , the pmos pull-up transistor still conducts if the pin is driving high, preventing an external pull-up resist or from pulling the signal to 5.0-v. a cyclone ii device can drive a 5.0-v lvttl device by connecting the v ccio pins of the cyclone ii device to 3.3 v. this is because the output high voltage (v oh ) of a 3.3-v interface meets the minimum high-level voltage of 2.4-v of a 5.0-v lvttl de vice. (a cyclone ii device cannot drive a 5.0-v lvcmos device.) because the cyclone ii devices are 3. 3-v, 64- and 32-bit, 66- and 33-mhz pci and 64-bit 133-mhz pci-x complian t, the input circuitry accepts a maximum high-level input voltage (v ih ) of 4.1-v. to drive a cyclone ii device with a 5.0-v device, you must connect a resistor (r 2 ) between the cyclone ii device and the 5.0-v device. see figure 10?21 . 1.5-v differential hstl class ii (3) 16 (4) lvds, rsds and mini-lvds 12 12 notes to table 10?12 : (1) the dc power specification of each i/o standard depend s on the current sourcing and sinking capabilities of the i/o buffer programmed with that standard, as well as the load being driven. lvttl and lvcmos, and 2.5-, 1.8-, and 1.5-v outputs are not included in the static power calculations because they normally do not have resistor loads in real applications. the voltage swing is rail-to-rail with capacitive load only. there is no dc current in the system. (2) this i pin value represents the dc current specification for the default current strength of the i/o standard. the i pin varies with programmable drive strength and is the same as the drive strength as set in quartus ii software. see the cyclone ii architecture chapter in volume 1 of the cyclone ii device handbook for more information on the programmable drive strength feature of voltage referenced i/o standards. (3) the current value obtained for differential hstl and diff erential sstl standards is per pin and not per differential pair, as opposed to the per-pair current value of lvds standard. (4) this i/o standard is only su pported for clock input pins and pll_out pins. table 10?12. cyclone ii i/o standard dc current specification (preliminary) (part 2 of 2) i/o standard i pin (ma) top & bottom banks side banks
altera corporation 10?35 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices figure 10?21. driving a cyclone ii de vice with a 5.0-volt device if v ccio is between 3.0 v and 3.6 v and th e pci clamping diode is enabled, the voltage at point b in figure 10?21 is 4.3 v or less. to limit large current draw from the 5.0-v device, r 2 should be small enough for a fast signal rise time and large enough so that it does not violate the high-level output current (i oh ) specifications of the devices driving the trace. the pci clamping diode in the cyclone ii device can support 25 ma of current. to compute the required value of r 2 , first calculate the model of the pull-up transistors on the 5.0-v device. this output resistor (r 1 ) can be modeled by dividing the 5.0-v device supply voltage (v cc ) by the i oh :r 1 =v cc /i oh . figure 10?22 shows an example of typical ou tput drive characteristics of a 5.0-v device. 5.0 v 0.25 v v cc model as r 1 r 2 v ccio 5.0 v device cyclone ii device i i pci clamp v ccio 3.0 - 3.4 v 0.25 v b
10?36 altera corporation cyclone ii device handbook, volume 1 february 2007 conclusion figure 10?22. output drive charac teristics of a 5.0-v device as shown above, r 1 = 5.0-v/135 ma. 1 the values shown in data sheets usually reflect typical operating conditions. subtract 20% from the data sheet value for guard band. this subtraction when applied in the example in figure 10?22 gives r 1 a value of 30 . r 2 should be selected so that it does not violate the driving device?s i oh specification. for example, if the device has a maximum i oh of 8 ma, given that the pci clamping diode, v in = v ccio + 0.7-v = 3.7-v, and the maximum supply load of a 5.0-v device (v cc ) is 5.25-v, the value of r 2 can be calculated as follows: this analysis assumes worst case conditions. if your system does not have a wide variation in voltage-supply levels, you can adjust these calculations accordingly. 1 because 5.0-v device tolerance in cyclone ii devices requires use of the pci clamp, and this clamp is activated during configuration, 5.0-v signals may not be driven into the device until it is configured. conclusion cyclone ii device i/o capabilities enable you to keep pace with increasing design complexity utilizing a low-cost fpga device family. support for i/o standards including sstl and lvds compatibility allow cyclone ii devices to fit in to a wide variety of a pplications. the quartus ii typical i o ou t pu t cu rr en t (ma) v o ou t pu t vol t age (v) 0 30 60 90 12345 120 150 135 v cci n t = 5.0 v v ccio = 5.0 v i ol i oh r 2 = (5.25 v ? 3.7 v) ? (8 ma 30 ) = 164 8 ma
altera corporation 10?37 february 2007 cyclone ii device handbook, volume 1 selectable i/o standards in cyclone ii devices software makes it easy to use these i/o standards in cyclone ii device designs. after design compilation, the software also provides clear, visual representations of pads and pins and the selected i/o standards. taking advantage of the support of these i/o standards in cyclone ii devices allows you to lower your design costs without compromising design flexibility or complexity. more information for more information on cyclone ii de vices, see the following resources: section i , cyclone ii device family data sheet of the cyclone ii device handbook an 75: high-speed board designs references for more information on the i/o standa rds referred to in this document, see the following sources: stub series terminated logic for 2.5-v (sstl-2), jesd8-9a, electronic industries as sociation, december 2000. 1.5-v +/- 0.1-v (normal range) and 0.9-v - 1.6-v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuits, jesd8-11, electronic industries association, october 2000. 1.8-v +/- 0.15-v (normal range) and 1.2-v - 1.95-v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuits, je sd8-7, electronic industries association, february 1997. 2.5-v +/- 0.2-v (normal range) and 1.8-v to 2.7-v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuits, je sd8-5, electronic industries association, october 1995. interface standard for nominal 3-v/ 3.3-v supply digital integrated circuits, jesd8-b, electronic industries association, september 1999. pci local bus specification, revision 2.2, pci special interest group, december 1998. electrical characterist ics of low voltage differential signaling (lvds) interface circuits, ansi/t ia/eia-644, american national standards institute/telecommunications industry/electronic industries association, october 1995.
10?38 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history document revision history table 10?13 shows the revision history for this document. table 10?13. document revision history date & document version changes made summary of changes february 2007 v2.3 added document revision history. updated ?introduction? and its feetpara note. updated note (2) in table 10?4 . updated ?differential lvpecl? section. updated ?differential pad placement guidelines? section. updated ?output pads? section. added new section ?5.0-v device compatibility? with two new figures. added reference detail for esd specifications. added information about differential placement restrictions ap plying only to pins in the same bank. added information that cyclone ii device supports lvds on clock inputs at 3.3v v ccio . added more information on dc placement guidelines. added information stating sstl and hstl outputs can be closer than 2 pads from v ref .. added 5.0 device tolerence solution. november 2005 v2.1 updated tables 10?2 and 10?3 . added pci express information. updated table 10?6 . july 2005 v2.0 updated table 10?1 . november 2004 v1.1 updated table 10?7 . june 2004 v1.0 added document to the cyclone ii device handbook.
altera corporation 11?1 february 2007 11. high-speed differential interfaces in cyclone ii devices introduction from high-speed backpl ane applications to high-end switch boxes, low-voltage differential signaling (lvds) is the technology of choice. lvds is a low-voltage differential signaling standard, allowing higher noise immunity than si ngle-ended i/o technolo gies. its low-voltage swing allows for high-speed data transfers, low power consumption, and reduced electromagnetic interference (e mi). lvds i/o signaling is a data interface standard defined in th e tia/eia-644 and ieee std. 1596.3 specifications. the reduced swing differential signaling (rsds) and mini-lvds standards are derivatives of the lvds standard. the rsds and mini-lvds i/o standards are similar in electrical characteristics to lvds, but have a smaller voltage swing and therefore provide increased power benefits and reduced emi. national semiconductor corporation and texas instruments introduced the rsds and mini-lvds specifications, respectively. curr ently, many designers use these specifications for flat panel display links between the controller and the drivers that drive display column drivers. cyclone ? ii devices support the rsds and mini-lvds i/o standards at speeds up to 311 megabits per second (mbps) at the transmitter. altera ? cyclone ii devices can transmit and receive data through lvds signals at a data rate of up to 640 mbps and 805 mbps, respectively. for the lvds transmitter and receiver, the cyclone ii device?s input and output pins support serialization an d deserialization through internal logic. this chapter describes how to use cy clone ii i/o pins for differential signaling and contains the following topics: cyclone ii high-speed i/o banks cyclone ii high-speed i/o interface lvds, rsds, mini-lvds, lvpecl, differential hstl, and differential sstl i/o standards support in cyclone ii devices high-speed i/o timing in cyclone ii devices design guidelines cyclone ii high- speed i/o banks cyclone ii device i/o banks are shown in figures 11?1 and 11?2 . the ep2c5 and ep2c8 devices offer four i/o banks and ep2c15, ep2c20, ep2c35, ep2c50, and ep2c70 devices of fer eight i/o banks. a subset of cii51011-2.2
11?2 altera corporation cyclone ii device handbook, volume 1 february 2007 cyclone ii high-speed i/o banks pins in each i/o bank (on both rows and columns) support the high- speed i/o interface. cycl one ii pin tables list the pins that support the high-speed i/o interface. figure 11?1. i/o banks in ep2c5 & ep2c8 devices notes to figure 11?1 : (1) the lvpecl i/o standard is only su pported on clock input pins. this i/o standard is not supported on output pins. (2) the differential sstl-18 and sstl-2 i/o standards are only supported on clock inpu t pins and pll output clock pins. (3) the differential 1.8-v and 1.5-v hstl i/o standards are only supported on clock input pins and pll output clock pins. i/o bank 2 i/o bank 3 i/o bank 4 i/o bank 1 all i/o banks support 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos lvds rsds mini-lvds lvpecl (1) sstl-2 class i and ii sstl-18 class i hstl-18 class i hstl-15 class i differential sstl-2 (2) differential sstl-18 (2) differential hstl-18 (3) differential hstl-15 (3) i/o bank 3 also supports the 3.3-v pci & pci- x i/o standards i/o bank 1 also supports the 3.3-v pci & pci-x i/o standards individual power bus i/o bank 2 also supports the sstl-18 class ii, hstl-18 class ii, & hstl-15 class ii i/o standards i/o bank 4 also supports the sstl-18 class ii, hstl-18 class ii, & hstl-15 class ii i/o standards
altera corporation 11?3 february 2007 cyclone ii device handbook, volume 1 high-speed differential interfaces in cyclone ii devices figure 11?2. i/o banks in ep2c15, ep2c 20, ep2c35, ep2c50 & ep2c70 devices notes to figure 11?2 : (1) the lvpecl i/o standard is only su pported on clock input pins. this i/o standard is not supported on output pins. (2) the differential sstl-18 and sstl-2 i/o standards are only supported on clock inpu t pins and pll output clock pins. (3) the differential 1.8-v and 1.5-v hstl i/o standards are only supported on clock input pins and pll output clock pins. cyclone ii high-speed i/o interface cyclone ii devices provide a multi- protocol interface that allows communication between a variety of i/o standards, including lvds, lvpecl, rsds, mini-lvds, differential hstl, and differential sstl. this feature makes the cyclone ii device family ideal for applications that require multiple i/o standards, such as protocol translation. i/o bank 2 regular i/o block bank 8 regular i/o block bank 7 i/o bank 3 i/o bank 4 i/o bank 1 i/o bank 5 i/o bank 6 individual power bus all i/o banks support 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos lvds rsds mini-lvds lvpecl (1) sstl-2 class i and ii sstl-18 class i hstl-18 class i hstl-15 class i differential sstl-2 (2) differential sstl-18 (2) differential hstl-18 (3) differential hstl-15 (3) i/o banks 3 & 4 also support the sstl-18 class ii, hstl-18 class ii, & hstl-15 class ii i/o standards i/o banks 7 & 8 also support the sstl-18 class ii, hstl-18 class ii, & hstl-15 class ii i/o standards i/o banks 5 & 6 also support the 3.3-v pci & pci-x i/o standard s i/o banks 1 & 2 also support the 3.3-v pci & pci-x i/o standards
11?4 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o standards support you can use i/o pins and internal lo gic to implement a high-speed i/o receiver and transmitter in cyclone ii devices. cyclone ii devices do not contain dedicated seriali zation or deserialization circuitry. therefore, shift registers, internal global phase-locked loops (plls), and i/o cells are used to perform serial-to-parallel conversions on incoming data and parallel-to-serial conver sion on outgoing data. i/o standards support this section provides information on the i/o standards that cyclone ii devices support. lvds standard support in cyclone ii devices the lvds i/o standard is a high-sp eed, low-voltage swing, low power, and general purpose i/o interface standard. the cyclone ii device meets the ansi/tia/eia-644 standard. i/o banks on all four sides of the cyclone ii device support lvds channels. see the pin tables on the alte ra web site for the number of lvds channels supported throughout different family members. cyclone ii lvds receivers (input) support a data rate of up to 805 mbps while lvds transmitters (output) support up to 640 mbps. the maximum internal clock frequency for a receiver and for a transmitter is 402.5 mhz. the maximum input data rate of 805 mb ps and the maximum output data rate of 640 mbps is only achieved when ddio registers are used. the lvds standard does not require an input reference voltage; however, it does require a 100- termination resistor between the two signals at the input buffer. f for lvds data rates in cyclone ii devices with different speed grades, see the dc characteristics & timing specifications chapter of the cyclone ii device handbook . table 11?1 shows lvds i/o specifications. table 11?1. lvds i/o specifications (part 1 of 2) note (1) symbol parameter condition min typ max units v ccint supply voltage 1.15 1.2 1.25 v v ccio i/o supply voltage 2.375 2.5 2.625 v v od differential output voltage r l = 100 250 600 mv v od change in v od between h and l r l = 100 50 mv v os output offset voltage r l = 100 1.125 1.25 1.375 v
altera corporation 11?5 february 2007 cyclone ii device handbook, volume 1 high-speed differential interfaces in cyclone ii devices lvds receiver & transmitter figure 11?3 shows a simple point-to-point lvds application where the source of the data is an lvds transmitter. these lvds signals are typically transmitted over a pair of printed circuit board (pcb) traces, but a combination of a pcb trace, conne ctors, and cables is a common application setup. figure 11?3. typical lvds application figures 11?4 and 11?5 show the signaling levels for lvds receiver inputs and transmitter outputs, respectively. v id input differential voltage (single-ended) 0.1 0.65 v v icm input common mode voltage 0.1 2.0 v v os change in v os between h and l r l = 100 50 mv r l receiver differential input resistor 90 100 110 note to ta b l e 11 ? 1 : (1) the specifications apply at the resistor network output. table 11?1. lvds i/o specifications (part 2 of 2) note (1) symbol parameter condition min typ max units transmitting device cyclone ii device 100 cyclone ii logic array 170 100 120 120 input buffer out p ut buffer receiving device txout + txout - rxin + rxin - txout + txout - rxin + rxin -
11?6 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o standards support figure 11?4. receiver input waveforms for the lvds differential i/o standard note to figure 11?4 : (1) the p ? n waveform is a function of the positive channel (p) and the negative channel (n). figure 11?5. transmitter output waveform for the lvds differential i/o standard note (2) notes to figure 11?5 : (1) the v od specifications apply at the resistor network output. (2) the p ? n waveform is a function of the positive channel (p) and the negative channel (n). differential waveform (mathematical function of positive & negative channel) v id v id v id 0 v p ? n (1) single-ended waveform positive channel (p) = v oh negative channel (n) = v o l ground v id v icm differential waveform (mathematical function of positive & negative channel) v od v od 0 v p ? n (2) single-ended waveform positive channel (p) = v oh negative channel (n) = v ol ground v od v os
altera corporation 11?7 february 2007 cyclone ii device handbook, volume 1 high-speed differential interfaces in cyclone ii devices rsds i/o standard support in cyclone ii devices the rsds specification is used in chip-to-chip applications between the timing controller and the column drivers on display panels. cyclone ii devices meet the national semicond uctor corporation rsds interface specification and support the rsds output standard. table 11?2 shows the rsds electrical characteristics for cyclone ii devices. figure 11?6 shows the rsds transmitte r output signal waveforms. figure 11?6. transmitter output si gnal level waveforms for rsds note (1) notes to figure 11?6 : (1) the v od specifications apply at the resistor network output. (2) the p ? n waveform is a function of the positive channel (p) and the negative channel (n). table 11?2. rsds electrical charac teristics for cyclone ii devices note (1) symbol parameter condition min typ max unit v ccio output supply voltage 2.375 2.5 2.625 v v od (2) differential output voltage r l =100 100 600 mv v os (3) output offset voltage r l = 100 1.125 1.25 1.375 v t r /t f transition time 20% to 80% 500 ps notes to ta b l e 11 ? 2 : (1) the specifications apply at the resistor network output. (2) v od = v oh - v ol . (3) v os = (v oh + v ol ) / 2. sin g le-ended waveform differential waveform (mathematical function of positive & ne g ative channel) positi v e channel (p) = v oh n egati v e channel (n) = v ol gro u nd v od v od v od v os 0 v p ? n (2)
11?8 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o standards support designing with rsds cyclone ii devices support the rsds output standard using the lvds i/o buffer types. for tr ansmitters, the lvds output buffer can be used with the external resistor network shown in figure 11?7 . figure 11?7. rsds resistor network note (1) note to figure 11?7 : (1) r s = 120 and r p =170 . f for more information on the rsds i/o standard, see the rsds specification from the nation al semiconductor web site (www.national.com) . a resistor network is required to attenuate the lvds output voltage swing to meet the rsds specifications. the resistor network values can be modified to reduce power or improve the noise margin. the resistor values chosen should sati sfy the following equation: additional simulations using the ib is models should be performed to validate that custom resistor values meet the rsds requirements. single resistor rsds solution the external single resistor solution reduces the external resistor count while still achieving the required signaling level for rsds. to transmit the rsds signal, an external resistor ( r p ) is connected in parallel between the two adjacent i/o pins on the board as shown in figure 11?8 . the recommended value of the resistor r p is 100 . rsds receive r r l = 100 50 cyclone ii device resistor network 1 inch lvds transmitter r p 50 + = r p 2 r s r p 2 50 r s
altera corporation 11?9 february 2007 cyclone ii device handbook, volume 1 high-speed differential interfaces in cyclone ii devices figure 11?8. rsds single resistor network note (1) note to figure 11?8 : (1) r p = 100 . rsds software support when designing for the rsds i/o standard, assign the rsds i/o standard to the i/o pins intended for rsds in the quartus ? ii software. contact altera applicatio ns for reference designs. mini-lvds standard support in cyclone ii devices the mini-lvds specification defines it s use in chip-to-chip applications between the timing controller and th e column drivers on display panels. cyclone ii devices meet the texas instruments mini-lvds interface specification and support the mini-lvds output standard. table 11?3 shows the mini-lvds electrical characteristics for cyclone ii devices. rsds receive r r l = 100 50 cyclone ii device resistor network 1 inch lvds transmitter r p 50 table 11?3. mini-lvds electrical char acteristics for cyclone ii devices note (1) symbol parameters condition min typ max units v ccio output supply voltage 2.375 2.5 2.625 v v od (2) differential output voltage r l = 100 300 600 mv v os (3) output offset voltage r l = 100 1125 1250 1375 mv t r / t f transition time 20% to 80% 500 ps notes to ta b l e 11 ? 3 : (1) the v od specifications apply at the resistor network output. (2) v od = v oh ? v ol . (3) v os = (v oh + v ol ) / 2.
11?10 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o standards support figure 11?9 shows the mini-lvds receiv er and transmitter signal waveforms. figure 11?9. transmitter out put signal level wave forms for mini-lvds note (1) note to figure 11?9 : (1) the v od specifications apply at the resistor network output. designing with mini-lvds similar to rsds, cyclone ii device s support the mini-lvds output standard using the lvds i/o buffer types. for transmitters, the lvds output buffer can be used with the external resistor network shown in figure 11?10 . the resistor values chosen sh ould satisfy the equation on page 11-8. v od v od 0 v differential waveform single-ended waveform positive channel (p) = v oh negative channel (n) = v ol ground v od v os
altera corporation 11?11 february 2007 cyclone ii device handbook, volume 1 high-speed differential interfaces in cyclone ii devices figure 11?10. mini-lvds resistor network note to figure 11?10 : (1) r s =120 and r p =170 . mini-lvds software support when designing for the mini-lvds i/ o standard, assign the mini-lvds i/o standard to the i/o pins intend ed for mini-lvds in the quartus ii software. contact altera applic ations for reference designs. lvpecl support in cyclone ii the lvpecl i/o standard is a differen tial interface standard requiring a 3.3-v v ccio and is used in applications involving video graphics, telecommunications, data communicati ons, and clock distribution. the high-speed, low-voltage swing lvpecl i/o standard uses a positive power supply and is similar to lvds. however, lvpecl has a larger differential output voltage swing th an lvds. cyclone ii devices support the lvpecl input standard at the clock input pins only. table 11?4 shows the lvpecl electrical characteristics for cyclone ii devices. figure 11?11 shows the lvpecl i/o interface. mini-lvds receive r r l = 100 50 cyclone ii device resistor network 1 inch lvds transmitter r s r p r s 50 table 11?4. lvpecl electrical charac teristics for cyclone ii devices symbol parameters condition min typ max units v ccio output supply voltage 3.135 3.3 3.465 v v ih input high voltage 2,100 2,880 mv v il input low voltage 0 2,200 mv v id differential input voltage peak to peak 100 600 950 mv
11?12 altera corporation cyclone ii device handbook, volume 1 february 2007 i/o standards support figure 11?11. lvpecl i/o interface differential sstl support in cyclone ii devices the differential sstl i/o standard is a memory bus standard used for applications such as high-speed double data rate (ddr) sdram interfaces. the differential sstl i/o standard is similar to voltage referenced sstl and requires two diff erential inputs with an external termination voltage (v tt ) of 0.5 v ccio to which termination resistors are connected. a 2.5-v output source vo ltage is required for differential sstl-2, while a 1.8-v output source voltage is required for differential sstl-18. the differential sstl outp ut standard is only supported at pllclkout pins using two single-e nded sstl output buffers programmed to have opposite polarity. the differential sstl input standard is supported at the global clock ( gclk ) pins only, treating differential inputs as two single-ended sstl, and only decoding one of them. f for sstl signaling char acteristics, see the dc characteristics & timing specification chapter and the selectable i/o standard s in cyclone ii devices chapter in volume 1 of the cyclone ii device handbook . figures 11?12 and 11?13 show the differential sstl class i and ii interfaces, respectively. lvds transmitter cyclone ii receiver 100 z = 50 z = 50
altera corporation 11?13 february 2007 cyclone ii device handbook, volume 1 high-speed differential interfaces in cyclone ii devices figure 11?12. differential ss tl class i interface figure 11?13. differential ss tl class ii interface differential hstl support in cyclone ii devices the differential hstl ac and dc spec ifications are the same as the hstl single-ended specifications. the differential hstl i/o standard is available on the gclk pins only, treating differen tial inputs as two single- ended hstl, and only decoding one of them. the differential hstl output i/o standard is only supported at the pllclkout pins using two single-ended hstl output buffers with the second output programmed as inverted. the standard requires two differential inputs with an external termination voltage (v tt ) of 0.5 v ccio to which termination resistors are connected. f for the hstl signaling ch aracteristics, see the dc characteristics & timing specifications chapter and the selectable i/o stan dards in cyclone ii devices chapter in volume 1 of the cyclone ii device handbook. output buffer receiver z 0 = 50 50 50 z 0 = 50 v tt v tt 25 25 output buffer receiver z 0 = 50 50 50 z 0 = 50 v tt v tt 50 50 v tt v tt 25 25
11?14 altera corporation cyclone ii device handbook, volume 1 february 2007 high-speed i/o timing in cyclone ii devices figures 11?14 and 11?15 show differential hstl class i and ii interfaces, respectively. figure 11?14. differential hstl class i interface figure 11?15. differential hs tl class ii interface high-speed i/o timing in cyclone ii devices this section discusses the timing budget, waveforms, and specifications for source-synchronous signaling in cyclone ii devices. lvds, lvpecl, rsds, and mini-lvds i/o standards enable high-speed data transmission. timing for these high-speed signals is based on skew between the data and the clock signals. high-speed differential data transmis sion requires timing parameters provided by integrated circuit (ic) vendors and requires consideration of board skew, cable skew, and clock jitter. this section provides details on high-speed i/o standards timing parameters in cyclone ii devices. output buffer receiver z 0 = 50 50 50 z 0 = 50 v tt v tt output buffer receiver z 0 = 50 50 50 z 0 = 50 v tt v tt 50 50 v tt v tt
altera corporation 11?15 february 2007 cyclone ii device handbook, volume 1 high-speed differential interfaces in cyclone ii devices table 11?5 defines the parameters of the timing diagram shown in figure 11?16 . figure 11?17 shows the cyclone ii hi gh-speed i/o timing budget. figure 11?16. high-speed i/o timing diagram table 11?5. high-speed i/o timing definitions parameter symbol description transmitter channel-to- channel skew (1) tccs the timing difference between the fastest and slowest output edges, including t co variation and clock skew. the clock is included in the tccs measurement. sampling window sw the period of time during which the data must be valid in order for you to capture it correctly. the setup and hold times determine the ideal strobe position within the sampling window. t sw =t su +t hd + pll jitter. receiver input skew margin rskm rskm is defined by the total margin left after accounting for the sampling window and tccs. the rskm equation is: rskm = (tui ? sw ? tccs) / 2. input jitter tolerance (peak- to-peak) allowed input jitter on the input clock to the pll that is tolerable while maintaining pll lock. output jitter (peak-to-peak) peak-to- peak output jitter from the pll. note to ta b l e 11 ? 5 : (1) the tccs specification applies to the entire bank of lvds as long as the serdes logic are placed within the lab adjacent to the output pins. samplin g window (sw) time unit interval (tui) rskm tccs rskm tccs internal clock external input clock receiver input data
11?16 altera corporation cyclone ii device handbook, volume 1 february 2007 design guidelines figure 11?17. cyclone ii high- speed i/o timing budget note (1) note to figure 11?17 : (1) the equation for the high-speed i/o timing budget is: period = 0.5/tccs + rskm + sw + rskm + 0.5/tccs. design guidelines this section provides guidelines for designing with cyclone ii devices. differential pad placement guidelines to maintain an acceptable noise level on the v ccio supply, there are restrictions on placement of single -ended i/o pins in relation to differential pads. f see the guidelines in the selectable i/o standards in cyclone ii devices chapter in volume 1 of the cyclone ii device handbook for placing single- ended pads with respect to differ ential pads in cyclone ii devices. board design considerations this section explains how to get the optimal performance from the cyclone ii i/o interface and ensure fi rst-time success in implementing a functional design with optimal signal quality. the critical issues of controlled impedance of traces and connectors, differential routing, and termination techniques must be cons idered to get the best performance from the ic. the cyclone ii device gene rates signals that travel over the media at frequencies as high as 805 mbps. use the following general guidelines for improved signal quality: base board designs on controlled differential impedance. calculate and compare all parameters such as trace width, trac e thickness, and the distance between two differential traces. internal clock period rskm 0.5 tccs rskm 0.5 tccs sw
altera corporation 11?17 february 2007 cyclone ii device handbook, volume 1 high-speed differential interfaces in cyclone ii devices maintain equal distance between traces in lvds pairs, as much as possible. routing the pair of traces close to each other maximizes the common-mode rejection ratio (cmrr). longer traces have more inductan ce and capacitance. these traces should be as short as possible to limit signal in tegrity issues. place termination resistors as close to receiver input pins as possible. use surface mount components. avoid 90 or 45 corners. use high-performance connectors. design backplane and card traces so that trace impedance matches the connector?s and/or th e termination?s impedance. keep equal number of vias for both signal traces. create equal trace lengths to avoi d skew between signals. unequal trace lengths result in misplaced crossing points and decrease system margins as the channel-to-channel skew (tccs) value increases. limit vias because they cause discontinuities. use the common bypass capacitor va lues such as 0.001, 0.01, and 0.1 f to decouple the high-speed pll power and ground planes. keep switching transistor-to-tran sistor logic (ttl) signals away from differential signals to avoid possible noise coupling. do not route ttl clock signals to areas under or above the differential signals. analyze system-level signals. for pcb layout guidelines, see an 224: high-speed board layout guidelines. conclusion cyclone ii differential i /o capabilities enable you to keep pace with increasing design complexity. su pport for i/o standards including lvds, lvpecl, rsds, mini-lvds, differential sstl and differential hstl allows cyclone ii de vices to fit into a wide variety of applications. taking advantage of these i/o capabi lities and cyclone ii pricing allows you to lower your design costs whil e remaining on the cutting edge of technology.
11?18 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history document revision history table 11?6 shows the revision history for this document. table 11?6. document revision history date & document version changes made summary of changes february 2007 v2.2 added document revision history. added note (1) to table 11?1 . updated figure 11?5 and added note (1) added note (1) to table 11?2 . updated figure 11?6 and added note (1) added note (1) to table 11?3 . added note (1) to figure 11?9 . added information stating lvds/rsds/mini-lvds i/o standards specifications apply at the external resistors network output. november 2005 v2.1 updated table 11?2 . updated figures 11?7 through 11?9 . added resistor network solution for rsds. updated note for mini-lvds resistor network table. july 2005 v2.0 updated ?i/o standards support? section. updated tables 11?1 through 11?3 . november 2004 v1.1 updated table 11?1 . updated figures 11?4 , 11?5 , 11?7 , and 11?9 . june 2004, v1.0 added document to the cyclone ii device handbook.
altera corporation section v?1 preliminary section v. dsp this section provides information for design and optimization of digital signal processing (dsp) functions an d arithmetic operations using the embedded multiplier blocks. this section includes the following chapter: chapter 12, embedded multipliers in cyclone ii devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the complete handbook.
section v?2 altera corporation preliminary revision history cyclone ii device handbook, volume 1
altera corporation 12?1 february 2007 12. embedded multipliers in cyclone ii devices introduction use cyclone ? ii fpgas alone or as digital signal processing (dsp) co-processors to improve price-to-performance ratios for dsp applications. you can implement high-performance yet low-cost dsp systems with the following cyclone ii device features and design support: up to 150 18 x 18 multipliers up to 1.1 mbit of on-chip embedded memory high-speed interface to external memory dsp intellectual property (ip) cores dsp builder interface to the mathworks simulink and matlab design environment dsp development kit, cyclone ii edition this chapter focuses on the cyclon e ii embedded multiplier blocks. cyclone ii devices have embedded multiplier blocks optimized for multiplier-intensive low-cost dsp applications. these embedded multipliers combined with the flexibility of programmable logic devices (plds), provide you with the ability to efficiently implement various cost sensitive dsp functions easily. consumer-based application systems such as digital television (dtv) and ho me entertainment systems typically require a cost effective solution for implementing multipliers to perform signal processing function s like finite impulse resp onse (fir) filters, fast fourier transform (fft) fu nctions, and discrete cosine transform (dct) functions. along with the embedded multipli ers, the m4k memory blocks in cyclone ii devices also support various soft multiplier implementations. these, in combination with the em bedded multipliers increase the available number of multipliers in cyclone ii devices and provide the user with a wide variety of implemen tation options and flexibility when designing their systems. f see the cyclone ii device family data sheet section in volume 1 of the cyclone ii device handbook for more information on cyclone ii devices. cii51012-1.2
12?2 altera corporation cyclone ii device handbook, volume 1 february 2007 embedded multiplier block overview embedded multiplier block overview each cyclone ii device has one to three columns of embedded multipliers that implement multip lication functions. figure 12?1 shows one of the embedded multiplier columns with the surrounding labs. each embedded multiplier can be configured to support one 18 18 multiplier or two 9 9 multipliers. figure 12?1. embedded multipliers arranged in columns with adjacent labs embedded multiplier embedded multiplier column 1 lab row
altera corporation 12?3 february 2007 cyclone ii device handbook, volume 1 embedded multipliers in cyclone ii devices the number of embedded multipliers per column and the number of columns available increases with device density. table 12?1 shows the number of embedded multipliers in each cyclone ii device and the multipliers that you can implement. in addition to the embedded multipliers, you can also implement soft multipliers using cyclone ii m4k memory blocks. the availa bility of soft multipliers increases the number of multipliers available within the device. table 12?2 shows the total number of multipliers available in cyclone ii devices using embedded multipliers and soft multipliers. table 12?1. number of embedded mult ipliers in cyclone ii devices device embedded multipliers 9 9 multipliers (1) 18 18 multipliers (1) ep2c5 13 26 13 ep2c8 18 36 18 ep2c20 26 52 26 ep2c35 35 70 35 ep2c50 86 172 86 ep2c70 150 300 150 note to table 12?1 : (1) each device has either the number of 9 9 or 18 18 multipliers shown. the total number of multipliers for each device is not the sum of all the multipliers. table 12?2. number of multipliers in cyclone ii devices device embedded multipliers (18 18) soft multipliers (16 16) (1) total multipliers (2) ep2c5 13 26 39 ep2c8 18 36 54 ep2c20 26 52 78 ep2c35 35 105 140 ep2c50 86 129 215 ep2c70 150 250 400 notes to ta b l e 1 2 ? 2 : (1) soft multipliers are implemented in sum of multiplication mode. the m4k memory blocks are configured with 18 -bit data widths to support 16-bit coefficients. the sum of the coefficients requ ires 18 bits of resolution to account for overflow. (2) the total number of multipliers may vary according to the multiplier mode used.
12?4 altera corporation cyclone ii device handbook, volume 1 february 2007 architecture see the cyclone ii memory blocks chapter in volume 1 of the cyclone ii device handbook for more information on cyclone ii m4k memory blocks. f refer to an 306: techniques for implementi ng multipliers in fpga devices for more information on soft multipliers. architecture each embedded multiplier consis ts of the following elements: multiplier stage input and output registers input and output interfaces figure 12?2 shows the multiplier block architecture. figure 12?2. multiplier block architecture note to figure 12?2 : (1) if necessary, you can send these signals through one register to match the data signal path. input registers you can send each multiplier input sign al into an input register or directly into the multiplier in 9- or 18-bit sections depending on the operational mode of the multiplier. you can send each multiplier input signal through a register independently of each other (e.g., you can send the multiplier?s clrn dq ena data a data b aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena data out embedded multiplier block output register input register
altera corporation 12?5 february 2007 cyclone ii device handbook, volume 1 embedded multipliers in cyclone ii devices data a signal through a register and se nd the data b signal directly to the multiplier). the following control signals are available to each register within the embedded multiplier: clock clock enable asynchronous clear all input and output registers within a single embedded multiplier are fed by the same clock, clock enab le, or asynchronous clear signal. multiplier stage the multiplier stage supports 9 9 or 18 18 multipliers as well as other smaller multipliers in between these configurations. see ?operational modes? on page 12?6 for details. depending on the data width or operational mode of the multiplier , a single embedded multiplier can perform one or two multip lications in parallel. each multiplier operand can be a un ique signed or unsigned number. two signals, signa and signb , control whether a multiplier?s input is a signed or unsigned value. if the signa signal is high, the data a operand is a signed number, and if the signa signal is low, the data a operand is an unsigned number. table 12?3 shows the sign of the multiplication result for the various operand sign representations. the result of the multiplication is signed if any one of the operands is a signed value. there is only one signa and one signb signal for each embedded multiplier. the signa and signb signals can be changed dynamically to modify the sign representa tion of the input operan ds at run time. you can send the signa and signb signals through a dedicated input register. the multiplier offers full precision regardless of the sign representation. table 12?3. multiplier sign representation data a data b result signa value logic level signb value logic level unsigned low unsigned low unsigned unsigned low signed high signed signed high unsigned low signed signed high signed high signed
12?6 altera corporation cyclone ii device handbook, volume 1 february 2007 operational modes 1 when the signa and signb signals are unused, the quartus ? ii software sets the multiplier to perform unsigned multiplication by default. output registers you can choose to register the embedded multiplier output using the output registers in 18- or 36-bit se ctions depending on the operational mode of the multiplier. the following control signals are available to each output register within the embedded multiplier: clock clock enable asynchronous clear all input and output registers within a single embedded multiplier are fed by the same clock, clock enab le, or asynchronous clear signal. f see the cyclone ii architecture chapter in volume 1 of the cyclone ii device handbook for more information on the embedded multiplier routing and interface. operational modes the embedded multiplier can be used in one of two operational modes, depending on the application needs: one 18-bit multiplier up to two 9-bit independent multipliers the quartus ii software includes mega functions used to control the mode of operation of the multipliers. after you have made the appropriate parameter settings using the megafunction?s megawizard ? plug-in manager, the quartus ii software autom atically configures the embedded multiplier. 1 the cyclone ii embedded multipliers can also be used to implement multiplier adder an d multiplier accumulator functions where the multiplier portion of the function is implemented using embedded multipliers and the adder or accumulator function is implem ented in logic elements (les). f for more information on megafunction and quartus ii support for cyclone ii embedded mu ltipliers, see the ?software support? section.
altera corporation 12?7 february 2007 cyclone ii device handbook, volume 1 embedded multipliers in cyclone ii devices 18-bit multipliers each embedded multiplier can be configured to support a single 18 18 multiplier for input wi dths from 10- to 18-bits. figure 12?3 shows the embedded multiplier configur ed to support an 18-bit multiplier. figure 12?3. 18-bit multiplier mode note to figure 12?3 : (1) if necessary, you can send these signals through one register to match the data signal path. all 18-bit multiplier inputs and result s can be independently sent through registers. the multiplier inputs can accept signed integers, unsigned integers or a combination of both . additionally, you can change the signa and signb signals dynamically and can send these signals through dedicated input registers. 9-bit multipliers each embedded multiplier can also be configured to support two 9 9 independent multipliers for input widths up to 9-bits. figure 12?4 shows the embedded multiplier co nfigured to support two 9-bit multipliers. clrn dq ena data a [17..0] data b [17..0] aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena data out [35..0] 18 18 multiplier embedded multiplier
12?8 altera corporation cyclone ii device handbook, volume 1 february 2007 operational modes figure 12?4. 9-bit multiplier mode note to figure 12?4 : (1) if necessary, you can send these signals through one register to match the data signal path. all 9-bit multiplier inputs and results can be independently sent through registers. the multiplier inputs can accept signed integers, unsigned integers, or a combination of both. each embedded multiplier only has one signa signal to control the sign repres entation of both data a inputs (one for each 9 9 multiplier) and one signb signal to control the sign representation of both data b inputs. therefore, all of the data a inputs feeding the same embedded multiplier must have the same sign representation. similarly, all of the data b inputs feeding the same embedded multiplier must have the same sign representation. clrn dq ena data a 0 [8..0] data b 0 [8..0] aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena data out 0 [17..0] 9 9 multiplier embedded multiplier clrn dq ena data a 1 [8..0] data b 1 [8..0] clrn dq ena clrn dq ena data out 1 [17..0] 9 9 multiplier
altera corporation 12?9 february 2007 cyclone ii device handbook, volume 1 embedded multipliers in cyclone ii devices software support altera provides two methods for im plementing multipliers in your design using embedded multiplier resources: instantiation and inference. both methods use the following three quartus ii megafunctions: lpm_mult altmult_add altmult_accum you can instantiate the megafunction s in the quartus ii software to use the embedded multipli ers. you can use the lpm_mult and altmult_add megafunctions to implement multipliers. additionally, you can use the altmult_add megafunctions to implement multiplier- adders where the embedded multiplier is used to implement the multiply function and the adder function is implemented in les. the altmult_accum megafunction implements multiply accumulate functions where the embedded multiplier implements the multiplier and the accumulator function is implemented in les. f see quartus ii on-line help for instru ctions on using the megafunctions and the megawizard plug-in manager. f for information on our complete dsp design and intellectual property offerings, see www.altera.com . you can also infer the megafunction s by creating an hdl design and synthesize it using quartus ii inte grated synthesis or a third-party synthesis tool that recognizes and infers the appropriate multiplier megafunction. using either method, the quartus ii software maps the multiplier functionality to the embedded multipliers during compilation. f see the synthesis section in volume 1 of the quartus ii handbook for more information. conclusion the cyclone ii device embedded multipliers are optimized to support multiplier-intensive dsp applications such as fir filters, fft functions and encoders. these embedded mul tipliers can be configured to implement multipliers of various bit widths up to 18-bits to suit a particular application resulting in efficient resource utilization and improved performance and data th roughput. the quartus ii software, together with the leonardospectrum and synplify software provide a complete and easy-to-use flow for implementing multiplier functions using embedded multipliers.
12?10 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history document revision history table 12?4 shows the revision history for this document. table 12?4. document revision history date & document version changes made summary of changes february 2007 v1.2 added document revision history. updated ?software support? section. removed reference to third-party synthesis tool: leonardospectrum and synplify. november 2005 v2.1 updated introduction. june 2004 v1.0 added document to the cyclone ii device handbook.
altera corporation section vi?1 preliminary section vi. configuration & test this section provides configuration information for all of the supported configuration schemes for cyclone ? ii devices. these configuration schemes use either a microprocessor, configuration device, or download cable. there is detailed information on how to design with altera ? configuration devices. the last chapter provides information on jtag support in cyclone ii devices. this section includes the following chapters: chapter 13, configuring cyclone ii devices chapter 14, ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the complete handbook.
section vi?2 altera corporation preliminary revision history cyclone ii device handbook, volume 1
altera corporation 13?1 february 2007 13. configuring cyclone ii devices introduction cyclone ? ii devices use sram cells to store configuration data. since sram memory is volatile, configurat ion data must be downloaded to cyclone ii devices each time the device powers up. you can use the active serial (as) configuration sc heme, which can operate at a dclk frequency up to 40 mhz, to configure cyclone ii devices. you can also use the passive serial (ps) and joint test action group (jtag)-based configuration schemes to configure cyclone ii devices. additionally, cyclone ii devices can receive a compressed configuration bitstream and decompress this data on-the-fly, reducing storage requirements and configuration time. this chapter explains the cyclone ii configuration features and describes how to configure cyclone ii devices using the supported configuration schemes. this chapter also includes configuration pin descriptions and the cyclone ii configuration file format. f for more information on setting device configuration options or creating configuration files, see the software settings chapter in the configuration handbook . cyclone ii configuration overview you can use the as, ps, and jtag configuration schemes to configure cyclone ii devices. you can select which configuration scheme to use by driving the cyclone ii device msel pins either high or low as shown in table 13?1 . the msel pins are powered by the v ccio power supply of the bank they reside in. the msel[1..0] pins have 9-k internal pull-down resistors that are always active. during power-on reset (por) and reconfiguration, the msel pins have to be at lvttl v il or v ih levels to be considered a logic low or logic high, respectively. therefore, to avoid any problems with detecting an incorrec t configuration scheme, you should connect the msel[] pins to the v ccio of the i/o bank they reside in and gnd without any pull-up or pull-down resistors. the msel[] pins should not be driven by a microprocessor or another device. cii51013-3.1
13?2 altera corporation cyclone ii device handbook, volume 1 february 2007 cyclone ii configuration overview you can download configuration data to cyclone ii fpgas with the as, ps, or jtag interfaces using the options in table 13?2 . table 13?1. cyclone ii configuration schemes configuration scheme msel1 msel0 as (20 mhz) 0 0 ps 0 1 fast as (40 mhz) (1) 10 jtag-based configuration (2) (3) (3) notes to ta b l e 1 3 ? 1 : (1) only the epcs16 and epcs64 devices support a dclk up to 40 mhz clock; other epcs devices support a dclk up to 20 mhz. refer to the serial configuration devices data sheet for more information. (2) jtag-based configuration takes precedence over other configuration schemes, which means msel pin settings are ignored. (3) do not leave the msel pins floating; connect them to v ccio or ground. these pins support the non-jtag configuration scheme used in production. if you are only using jtag configuration, you should connect the msel pins to ground. table 13?2. cyclone ii device configuration schemes configuration sc heme description as configuration configuration using serial configuration devices (epcs1, epcs4, epcs16 or epcs64 devices) ps configuration configuration using enhanced configuration devices (epc4, epc8, and epc16 devices), epc2 and epc1 configuration devices, an intelligent host (mic roprocessor), or a download cable jtag-based configuration configur ation via jtag pins using a download cable, an intelligent host (microprocessor), or the jam? standard test and programming language (stapl)
altera corporation 13?3 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices configuration file format table 13?3 shows the approximate uncompressed configuration file sizes for cyclone ii devices. to calculate th e amount of storage space required for multiple device configurations, add the file size of each device together. use the data in table 13?3 only to estimate the fi le size before design compilation. different configuration file formats, such as a hexadecimal ( .hex ) or tabular text file ( .ttf ) format, have different file sizes. however, for any specific version of the quartus ? ii software, any design targeted for the same device has the same uncompressed configuration file size. if compression is used, the file size can vary after each compilation since the compression ratio is dependent on the design. configuration data compression cyclone ii devices support configuration data decompression, which saves configuration memory space an d time. this feature allows you to store compressed configuration data in configuration devices or other memory and transmit this compress ed bitstream to cyclone ii devices. during configuration, the cyclone ii device decompresses the bitstream in real time and programs its sram cells. 1 preliminary data indicates that compression reduces configuration bitstream size by 35 to 55%. cyclone ii devices support deco mpression in the as and ps configuration schemes. decompression is not supported in jtag-based configuration. table 13?3. cyclone ii raw binary file (.rbf) sizes note (1) device data size (bits) data size (bytes) ep2c5 1,265,792 152,998 ep2c8 1,983,536 247,974 ep2c15 3,892,496 486,562 ep2c20 3,892,496 486,562 ep2c35 6,858,656 857,332 ep2c50 9,963,392 1,245,424 ep2c70 14,319,216 1,789,902 note to table 13?3 : (1) these values are preliminary.
13?4 altera corporation cyclone ii device handbook, volume 1 february 2007 configuration data compression although they both use the sa me compression algorithm, the decompression feature supported by cyclone ii devices is different from the decompression feature in enhanc ed configuration devices (epc16, epc8, and epc4 devices). the data decompression feature in the enhanced configuration de vices allows them to store compressed data and decompress the bitstream before tr ansmitting it to the target devices. in ps mode, you should use the cycl one ii decompression feature since sending compressed configuration da ta reduces configuration time. you should not use both the cyclone ii de vice and the enhanced configuration device decompression features simultaneously. the compression algorithm is not intend ed to be recursive and could expand the configuration file instead of compressing it further. you should use the cyclone ii de compression feature during as configuration if you need to save configuration memory space in the serial configuration device. when you enable compression, th e quartus ii software generates configuration files with compressed configuration data. this compressed file reduces the storage requirements in the configuration device or flash, and decreases the time needed to tran smit the bitstream to the cyclone ii device. the time required by a cyclone ii device to decompress a configuration file is less than the time needed to transmit the configuration data to the fpga. there are two methods to enable comp ression for cyclone ii bitstreams: before design compilation (in the compiler settings menu) and after design compilation (in the convert programming files window). to enable compression in the project's compiler settings, select device under the assignments menu to brin g up the settings window. after selecting your cyclone ii device open the device & pin options window, and in the general settings tab enable the check box for generate compressed bitstreams (see figure 13?1 ).
altera corporation 13?5 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices figure 13?1. enabling compression for cy clone ii bitstreams in compiler settings you can also use the following steps to enable compression when creating programming files from the conv ert programming files window. 1. click convert programming files (file menu). 2. select the programming file ty pe. only programmer object files ( .pof ), sram hexout, rbf, or ttf files support compression. 3. for pofs, select a configuration device. 4. select add file and add a cyclone ii sram object file(s) ( .sof ). 5. select the name of the file you added to the sof data area and click on properties . 6. check the compression check box.
13?6 altera corporation cyclone ii device handbook, volume 1 february 2007 active serial configuration (serial configuration devices) when multiple cyclone ii devices are cascaded, the compression feature can be selectively enabled for each device in the chain. figure 13?2 depicts a chain of two cyclone ii devices. the first cyclone ii device has compression enabled and therefore receives a compressed bitstream from the configuration device. the second cyclone ii device has the compression feature disabled and receives uncompressed data. figure 13?2. compressed & uncompressed configuration data in a programming file you can generate programming files (for example, pof files) for this setup in the quartus ii software. active serial configuration (serial configuration devices) in the as configuration scheme, cycl one ii devices are configured using a serial configuration device. these configuration devices are low-cost devices with non-volatile memory that feature a simple, four-pin interface and a small form factor . these features make serial configuration devices an ideal low-cost configuration solution. f for more information on serial configuration devices, see the serial configuration devices data sheet in the configuration handbook. nce gnd nceo decompression controller cyclone ii device nce nceo n.c. decompression controller cyclone ii device serial or enhanced configuration device serial data compressed uncompressed v cc 10 k
altera corporation 13?7 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices serial configuration devices provide a serial interface to access configuration data. during device co nfiguration, cyclone ii devices read configuration data via the serial interface, decompress data if necessary, and configure their sram cells. the fpga controls the configuration interface in the as configuration scheme , while the external host (e.g., the configuration device or microprocessor ) controls the interface in the ps configuration scheme. 1 the cyclone ii decompression feature is available when configuring your cyclone i i device using as mode. table 13?4 shows the msel pin settings when using the as configuration scheme. single device as configuration serial configuration devices have a four-pin interface: serial clock input ( dclk ), serial data output ( data ), as data input ( asdi ), and an active-low chip select ( ncs ). this four-pin interface connects to cyclone ii device pins, as shown in figure 13?3 . table 13?4. cyclone ii configuration schemes configuration scheme msel1 msel0 as (20 mhz) 0 0 fast as (40 mhz) (1) 10 note to table 13?4 : (1) only the epcs16 and epcs64 devices support a dclk up to 40 mhz clock; other epcs devices support a dclk up to 20 mhz. refer to the serial configuration devices data sheet for more information.
13?8 altera corporation cyclone ii device handbook, volume 1 february 2007 active serial configuration (serial configuration devices) figure 13?3. single device as configuration notes to figure 13?3 : (1) connect the pull-up re sistors to a 3.3-v supply. (2) cyclone ii devices use the asdo to asdi path to control the configuration device. (3) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed another device?s nce pin. upon power-up, the cyclone ii device goes through a por. during por, the device resets, holds nstatus and conf_done low, and tri-states all user i/o pins. after por, which ty pically lasts 100 ms, the cyclone ii device releases nstatus and enters configuration mode when the external 10-k resistor pulls the nstatus pin high. once the fpga successfully exits por, all user i/o pins continue to be tri-stated. cyclone ii devices have weak pull-up resistors on the user i/o pins which are on before and during configuration. f the value of the weak pull-up resis tors on the i/o pins that are on before and during configuration are available in the dc characteristics & timing specifications chapter of the cyclone ii device handbook . the configuration cycle consists of the reset, configuration, and initialization stages. data dclk ncs asdi data 0 dclk ncso asdo serial config u ration de v ice cyclone ii fpga 10 k 10 k v cc 10 k v cc v cc g n d nceo nce nstatus nco n fig co n f_do n e (2) msel1 msel0 g n d n .c. (1) (1) (1) v cc (3 )
altera corporation 13?9 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices reset stage when nconfig or nstatus are low, the device is in reset. after por, the cyclone ii device releases nstatus . an external 10-k pull-up resistor pulls the nstatus signal high, and the cyclone ii device enters configuration mode. 1 v ccint and v ccio of the banks where the configuration and jtag pins reside need to be fully powered to the appropriate voltage levels in order to begin the configuration process. configuration stage the serial clock ( dclk ) generated by the cyclon e ii device controls the entire configuration cycle and provides the timing for the serial interface. cyclone ii devices use an inte rnal oscillator to generate dclk . using the msel[] pins, you can select either a 20- or 40-mhz oscillator. although you can select either 20- or 40-mhz os cillator when designing with serial configuration devices, the 40-mhz oscillator provides faster configuration times. there is some variation in the internal oscillator frequency because of the process, temperature, and voltage conditions in cyclone ii devices. the internal oscillator is designed such that its maximum frequency is guaranteed to meet epcs device specifications. table 13?5 shows the as dclk output frequencies. in both as and fast as configuratio n schemes, the seri al configuration device latches input and control signals on the rising edge of dclk and drives out configuration data on the falling edge. cyclone ii devices drive out control signals on the falling edge of dclk and latch configuration data on the falling edge of dclk . in configuration mode, the cyclon e ii device enables the serial configuration device by driving its ncso output pin low, which connects to the chip select ( ncs ) pin of the configuratio n device. the cyclone ii device uses the serial clock ( dclk ) and serial data output ( asdo ) pins to send operation commands and/or re ad address signals to the serial table 13?5. as dclk output frequency note (1) oscillator selected minimum typical maximum units 40 mhz 20 26 40 mhz 20 mhz 10 13 20 mhz note to table 13?5 : (1) these values are preliminary.
13?10 altera corporation cyclone ii device handbook, volume 1 february 2007 active serial configuration (serial configuration devices) configuration device. the configuration device then provides data on its serial data output ( data ) pin, which connects to the data0 input of the cyclone ii device. after the cyclone ii device receives a ll the configuration bits, it releases the open-drain conf_done pin, which is then pulled high by an external 10-k resistor. also, the cyclone i i device stops driving the dclk signal. initialization begins only after the conf_done signal reaches a logic high level. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. all as configuration pins ( data0 , dclk , ncso , and asdo ) have weak internal pull-up resistors which are always active. after configuration, th ese pins are set as input tri-stated and are pulled high by the in ternal weak pull-up resistors. initialization stage in cyclone ii devices, the initiali zation clock source is either the cyclone ii 10-mhz (typical) internal oscillator (separat e from the as internal oscillator) or the optional clkusr pin. the internal oscillator is the default clock source for initialization. if the internal oscillator is used, the cyclone ii device provides itself with enough clock cycles for proper initialization. the advantage of using th e internal oscillator is you do not need to send additional clock cycles from an external source to the clkusr pin during the initialization stage. additionally, you can use the clkusr pin as a user i/o pin. if you want to delay the initialization of the device, you can use the clkusr pin option. using the clkusr pin allows you to control when your device enters user mode. the de vice can be delayed from entering user mode for an indefinite amou nt of time. when you enable the user supplied start-up clock option, the clkusr pin is the initialization clock source. supplying a clock on clkusr does not affect the configuration process. af ter all configuration data has been accepted and conf_done goes high, cyclone ii devices require 299 clock cycles to initialize properly and support a clkusr f max of 100 mhz.
altera corporation 13?11 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices cyclone ii devices offer an optional init_done pin which signals the end of initialization and the start of user mode with a low-to-high transition. the enable init_done output option is available in the quartus ii software from the general tab of the device & pin options window. if you use the init_done pin, an external 10-k pull-up resistor is required to pull the signal high when nconfig is low and during the beginning of configuration. once the optional bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the init_done pin is released and pulled high. this low-to-high transition si gnals that the fpga has entered user mode. if you do not use the init_done pin, the initialization period is complete after conf_done goes high and 299 clock cycles are sent to the clkusr pin or after the time t cf2um (see table 13?8 ) if the cyclone ii device uses the internal oscillator. user mode when initialization is complete, the fpga enters user mode. in user mode, the user i/o pins no longer have weak pull-up resistors and function as assigned in your design. when the cyclone ii device is in user mode, you can initiate reconfiguration by pulling the nconfig signal low. the nconfig signal should be low for at least 2 s. when nconfig is pulled low, the cyclone ii device is reset and enters the reset stage. the cyclone ii device also pulls nstatus and conf_done low and all i/o pins are tri-stated. once nconfig returns to a logic high level and nstatus is released by the cyclone ii device, reconfiguration begins. error during configuration if an error occurs during configurat ion, the cyclone ii device drives the nstatus signal low to indicate a data frame error, and the conf_done signal stays low. if you enable the auto-restart configuration after error option in the quartus ii software from the general tab of the device & pin options dialog box, the cyclone ii device resets the serial configuration device by pulsing ncso , releases nstatus after a reset time-out period (about 40 s), an d retries configuration. if the auto-restart configuration after error option is turned off, the external system must monitor nstatus for errors and then pull nconfig low for at least 2 s to restart configuration. 1 if you use the optional clkusr pin and the nconfig pin is pulled low to restart configuration during device initialization, ensure clkusr continues to toggle during the time nstatus is low (a maximum of 40 s).
13?12 altera corporation cyclone ii device handbook, volume 1 february 2007 active serial configuration (serial configuration devices) f for more information on co nfiguration issues, see the debugging configuration problems chapter of the configuration handbook and the fpga configuration troubleshooter on the altera web site ( www.altera.com ). multiple device as configuration you can configure multiple cyclone ii devices using a single serial configuration device. you can cascade multiple cyclone ii devices using the chip-enable ( nce ) and chip-enable-out ( nceo ) pins. connect the nce pin of the first device in the chain to ground and connect the nceo pin to the nce pin of the next de vice in the chain. use an external 10-k pull-up resistor to pull the nceo signal high to its v ccio level to help the internal weak pull-up resistor. when the fi rst device captures all of its configuration data from the bi tstream, it transitions its nceo pin low, initiating the configuration of the next device in the chain. you can leave the nceo pin of the last device unconnect ed or use it as a user i/o pin after configuration if the last devi ce in chain is a cyclone ii device. 1 the quartus ii software sets the cyclone ii device nceo pin as an output pin driving to ground by default. if the device is in a chain, and the nceo pin is connected to the next device?s nce pin, you must make sure that the nceo pin is not used as a user i/o pin after configuration. the software setting is in the dual-purpose pins tab of the device & pin options dialog box in quartus ii software. the first cyclone ii device in the ch ain is the configuration master and controls the configuration of the entire chain. select the as configuration scheme for the first cyclone ii device and the ps configuration scheme for the remaining cyclone ii devices (c onfiguration slav es). any other altera ? device that supports ps configurat ion can also be part of the chain as a configuration slave. in a multiple device chain, the nconfig , nstatus , conf_done , dclk , and data0 pins of each device in the chain are connected (see figure 13?4 ). figure 13?4 shows the pin connections for this setup.
altera corporation 13?13 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices figure 13?4. multiple device as configuration notes to figure 13?4 : (1) connect the pull-up resistors to a 3.3-v supply. (2) connect the pull-up resistor to the v ccio supply voltage of i/o bank that the nceo pin resides in. (3) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed another device?s nce pin. as shown in figure 13?4 , the nstatus and conf_done pins on all target fpgas are connected together with exte rnal pull-up resistors. these pins are open-drain bidirectional pins on the fpgas. when the first device asserts nceo (after receiving all of its configuration data), it releases its conf_done pin. however, the subsequent devices in the chain keep the conf_done signal low until they receive their configuration data. when all the target fpgas in the chain have received their configuration data and have released conf_done , the pull-up resistor pu lls this signal high, and all devices simultaneously enter initialization mode. data dclk ncs asdi data0 dclk ncso asdo serial configuration device cyclone ii fpga master device 10 k 10 k v cc v cc gnd nceo nce nstatus conf_done data0 dclk cyclone ii fpga slave device nceo nce nstatus conf_done 10 k v cc nconfig nconfig msel1 msel0 gnd v cc n.c. msel1 msel0 gnd (1) (1) (1) 10 k v cc (2) (3 ) v cc
13?14 altera corporation cyclone ii device handbook, volume 1 february 2007 active serial configuration (serial configuration devices) during initialization, the initialization clock source is either the cyclone ii 10 mhz (typical ) internal oscillator (separate from the as internal oscillator) or the optional clkusr pin. by default, the internal oscillator is the clock source for initia lization. if the internal oscillator is used, the cyclone ii device provides itself with enough clock cycles for proper initialization. the advantage of using the internal oscillator is you do not need to send additional clock cy cles from an external source to the clkusr pin during the initialization stage. you can also make use of the clkusr pin as a user i/o pin, which me ans you have an additional user i/o pin. if you want to delay the initialization of the devices in the chain, you can use the clkusr pin option. the clkusr pin allows you to control when your device enters user mode. this feature also allows you to control the order of when each device enters user mode by feeding a separate clock to each device?s clkusr pin. by using the clkusr pins, you can choose any device in the multiple device chain to enter user mode first and have the other devices enter user mode at a later time. different device families may require a different number of initialization clock cycles. therefore, if your multi ple device chain consists of devices from different families, the devices may enter user mode at a slightly different time due to the different n umber of initialization clock cycles required. however, if the number of initialization clock cycles is similar across different device families or if the devices are from the same family, then the devices enter user mode at the same time. see the respective device family handbook for more information about the number of initialization clock cycles required. if an error occurs at any point duri ng configuration, the fpga with the error drives the nstatus signal low. if you enable the auto-restart configuration after error option, the entire chai n begins reconfiguration after a reset time-out period (a maximum of 40 s). if the auto-restart configuration after error option is turned off, a microprocessor or controller must monitor nstatus for errors and then pulse nconfig low to restart configuration. the microprocessor or controller can pulse nconfig if it is under system control rather than tied to v cc . 1 while you can cascade cyclone ii devices, serial configuration devices cannot be cascaded or chained together. 1 if you use the optional clkusr pin and the nconfig is pulled low to restart configuration duri ng device initialization, make sure the clkusr pin continues to toggle while nstatus is low (a maximum of 40 s).
altera corporation 13?15 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices if the configuration bitstream size exceeds the capacity of a serial configuration device, you must select a larger configuration device and/or enable the compression feature. when configuring multiple devices, the size of the bitstream is the sum of the individual devices' configuration bitstreams. configuring multiple cyclone ii devices with the same design certain designs require you to configure multiple cyclone ii devices with the same design through a configurat ion bitstream or sof. you can do this through one of two methods, as described in this section. for both methods, the serial configuration devi ces cannot be cascaded or chained together. multiple sofs in the first method, two copies of th e sof file are stored in the serial configuration device. use the first copy to configure the master cyclone ii device and the second copy to configure all remaining slave devices concurrently. in this setup, the mast er cyclone ii device is in as mode, and the slave cyclone ii devices are in ps mode ( msel=01 ). see figure 13?5 . to configure four identical cyclone ii devices with the same sof file, connect the three slave devices for co ncurrent configuration as shown in figure 13?5 . the nceo pin from the master device drives the nce input pins on all three slave devices. connect the configuration device?s data and dclk pins to the cyclone ii device?s data and dclk pins in parallel. during the first configuration cycle, the master device reads its configuration data from the serial configuration device while holding nceo high. after completing its config uration cycle, the master drives nce low and transmits the second copy of the configuration data to all three slave devices, configuring them simultaneously. the advantage of using the setup in figure 13?5 is that you can have a different sof file for the cyclone ii master device. however, all the cyclone ii slave devices must be config ured with the same sof file. the sof files in this configuration meth od can be either compressed or uncompressed. 1 you can still use this method if the master and slave cyclone ii devices use the same sof.
13?16 altera corporation cyclone ii device handbook, volume 1 february 2007 active serial configuration (serial configuration devices) figure 13?5. multiple device as configuration when fp gas receive the same data with multiple sofs notes to figure 13?5 : (1) connect the pull-up resistors to a 3.3-v supply. (2) connect the pull-up resistor to the v ccio supply voltage of i/o bank that the nceo pin resides in. (3) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed another device?s nce pin. cyclone ii device master nstatus conf_done nconfig nce data 0 dclk ncso nceo msel0 msel1 asdo data dclk ncs asdi cyclone ii device slave n s tat u s conf_done nconfig nce n.c. data0 dclk nceo msel0 msel1 v cc cyclone ii device slave n s tat u s conf_done nconfig nce n.c. data0 dclk nceo msel0 msel1 v cc v cc cyclone ii device slave n s tat u s conf_done nconfig nce n.c. data0 dclk nceo msel0 msel1 v cc v cc v cc v cc v cc serial configuration device (1) (1) (1) (3) (4 ) (4 ) (4 ) 10 k 10 k 10 k 10 k
altera corporation 13?17 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices single sof the second method configures both the master and slave cyclone ii devices with the same sof. the seri al configuration device stores one copy of the sof file. this setup is shown in figure 13?6 where the master is setup in as mode, and the slave devices are setup in ps mode ( msel=01 ). you could setup one or more slave devices in the chain and all the slave devices are setup in the same way as shown in figure 13?6 . figure 13?6. multiple device as configuration when fpgas receive the same data with a single sof notes to figure 13?6 : (1) connect the pull-up resistors to a 3.3-v supply. (2) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed another device?s nce pin. in this setup, all the cyclone ii de vices in the chain are connected for concurrent configuration. this can reduce the as configuration time because all the cyclone ii devices are configured in one configuration cycle. connect the nce input pins of all the cyclone ii devices to ground. you can either leave the nceo output pins on all the cyclone ii devices unconnected or use the nceo output pins as normal user i/o pins. the data and dclk pins are connected in para llel to all the cyclone ii devices. cyclone ii de v ice master nstatus co n f_do n e nco n fig nce data0 dclk ncso nceo msel0 msel1 asdo data dclk ncs asdi cyclone ii de v ice sla v e 1 nstatus co n f_do n e nco n fig nce data0 dclk msel0 msel1 v cc v cc v cc v cc v cc serial config u ration de v ice (1) (1) (1) (3) b u ffe rs 10 k 10 k 10 k n .c. nceo (3) n .c. cyclone ii de v ice sla v e 2 nstatus co n f_do n e nco n fig nce data0 dclk msel0 msel1 v cc nceo (3 ) n .c.
13?18 altera corporation cyclone ii device handbook, volume 1 february 2007 active serial configuration (serial configuration devices) you should put a buffer before the data and dclk output from the master cyclone ii device to avoid signal strength and signal integrity issues. the buffer should not significantly change the data -to- dclk relationships or delay them with respect to other as signals ( asdi and ncs ). also, the buffer should only dr ive the slave cyclone ii devices, so that the timing between the mast er cyclone ii device and serial configuration device is unaffected. this configuration method supports both compressed and uncompressed sofs. therefore, if the configuration bitstream size exceeds the capacity of a serial configuration device, you can enable the compression feature in the sof file used or you can select a larger serial configuration device. estimating as configuration time the as configuration time is the time it takes to transfer data from the serial configuration device to th e cyclone ii device. the cyclone ii dclk output (generated from an internal osci llator) clocks this serial interface. as listed in table 13?5 , if you are using the 40-mhz oscillator, the dclk minimum frequency is 20 mhz (50 ns). therefore, the maximum configuration time estimate for an ep2c5 device (1,223,980 bits of uncompressed data) is: rbf size (maximum dclk period / 1 bit per dclk cycle) = estimated maximum configuration time 1,223,980 bits (50 ns / 1 bit) = 61.2 ms to estimate the typical config uration time, use the typical dclk period listed in table 13?5 . with a typical dclk period of 38.46 ns, the typical configuration time is 47.1 ms. enabling compression reduces the amount of configuration data that is transm itted to the cyclone ii device, which also reduces configuration time. on average, compression reduces configuration time by 50%.
altera corporation 13?19 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices programming serial configuration devices serial configuration devices are non-volatile, flash-memory-based devices. you can program thes e devices in-system using the usb-blaster? or byteblaster? ii download cable. alternatively, you can program them using the altera pr ogramming unit (apu), supported third-party programmers, or a mi croprocessor wi th the srunner software driver. you can use the as programming interface to program serial configuration devices in-system. during in-system programming, the download cable disables fpga access to the as interface by driving the nce pin high. cyclone ii devices are also held in reset by pulling the nconfig signal low. after programming is complete, the download cable releases the nce and nconfig signals, allowing the pull-down and pull-up resistor to drive gnd and v cc , respectively. figure 13?7 shows the download cable connections to the serial configuration device. f for more information on the usb-blaster download cable, see the usb-blaster usb port download cable data sheet . for more information on the byteblaster ii cable, see the byteblaster ii down load cable data sheet .
13?20 altera corporation cyclone ii device handbook, volume 1 february 2007 active serial configuration (serial configuration devices) figure 13?7. in-system programming of serial configuration devices notes to figure 13?7 : (1) connect these pull-up resistors to 3.3-v supply. (2) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed other device?s nce pin. (3) power up the byteblaster ii or usb blaster cable?s v cc with a 3.3-v supply. you can use the quartus ii software with the apu and the appropriate configuration device programmin g adapter to program serial configuration devices. all serial configuration devices are offered in an 8-pin or 16-pin small outline integrat ed circuit (soic) package and can be programmed using the plmsepc-8 adapter. data dclk ncs asdi data0 dclk ncso nce nco n fig nstatus nceo co n f_do n e asdo v cc v cc v cc v cc 10 k 10 k 10 k 10 k cyclone ii fpga serial config u ration de v ice pi n 1 msel1 msel0 g n d bytebla s te r ii o r u s b bla s te r 10-pi n male heade r (2 ) n .c. (1) (1) (1) (3) v cc
altera corporation 13?21 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices altera programming hardware (apu) or other third-party programming hardware can be used to program bl ank serial configuration devices before they are mounted onto pcbs. alternatively, you can use an on- board microprocessor to program the se rial configuration device on the pcb using c-based software drivers pr ovided by altera (i.e., the srunner software driver). a serial configuration device can be programmed in-system by an external microprocessor using srunner. srunner is a software driver developed for embedded serial configuration device programming, which can be easily customized to fi t in different embedded systems. srunner can read a raw programming data file ( .rpd ) and write to the serial configuration devices. the serial configuration device programming time using srunner is comparable to the programming time when using the quartus ii programmer. f for more information about srunner, see the srunner: an embedded solution for epcs programming white paper and the source code on the altera web site at www.altera.com. for more information on programming serial configuration devices, see the serial configuration devices data sheet in the configuration handbook . figure 13?8 shows the timing waveform for the as configuration scheme using a serial configuration device. figure 13?8. as configuration timing read address bit n ? 1 bit n bit 1 bit 0 299 cycles nstatus nconfig conf_done ncso dclk asdo data0 init_done user i/o user mode t cf2st1 t h t su t ch t cl tri-stated with internal pull-up resistor.
13?22 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration ps configuration you can use an altera configuration device, a download cable, or an intelligent host, such as a max ? ii device or microprocessor to configure a cyclone ii device with the ps scheme. in the ps scheme, an external host (configuration device, max ii device, embedded processor, or host pc) controls configuration. configuration data is input to the target cyclone ii devices via the data0 pin at each rising edge of dclk . 1 the cyclone ii decompression feat ure is fully available when configuring your cyclone ii device using ps mode. table 13?6 shows the msel pin settings when using the ps configuration scheme. single device ps configuration using a max ii device as an external host in the ps configuration scheme, yo u can use a max ii device as an intelligent host that controls the tr ansfer of configuration data from a storage device, such as flash memory, to the target cyclone ii device. configuration data can be stored in rbf, hex, or ttf format. figure 13?9 shows the configuration interface connections between the cyclone ii device and a max ii device for single device configuration. table 13?6. cyclone ii msel pi n settings for ps configuration schemes configuration scheme msel1 msel0 ps 0 1
altera corporation 13?23 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices figure 13?9. single device ps confi guration using an external host notes to figure 13?9 : (1) connect the pull-up resistor to a supply that provides an acceptable input signal for the device. v cc should be high enough to meet the vih specification of the i/o on the device and the external host. (2) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed other device?s nce pin. upon power-up, the cyclone ii device goes through a por, which lasts approximately 100 ms. during po r, the device resets, holds nstatus low, and tri-states all user i/o pins . once the fpga successfully exits por, all user i/o pins continue to be tri-stated. f the value of the weak pull-up resis tors on the i/o pins that are on before and during configuration can be found in the cyclone ii device handbook . the configuration cycle consists of three stages: reset, configuration, and initialization. reset stage while the cyclone ii device?s nconfig or nstatus pins are low, the device is in reset. to initiate configuration, the max ii device must transition the cyclone ii nconfig pin from low to high. 1 v ccint and v ccio of the banks where the configuration and jtag pins reside need to be fully powered to the appropriate voltage levels in order to begin the configuration process. when the cyclone ii nconfig pin transitions high, the cyclone ii device comes out of reset and releases the open-drain nstatus pin, which is then pulled high by an external 10-k pull-up resistor. once nstatus is released, the fpga is ready to receiv e configuration data and the max ii device can start the configuration at any time. external host (max ii device or microprocessor) conf_done nstatus nce data0 nconfig cyclone ii device memory addr data0 gnd msel1 v cc . (1) v cc . (1) 10 k 10 k gnd dclk nceo n.c. (2 ) msel0 v cc
13?24 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration configuration stage after the cyclone ii device?s nstatus pin transitions high, the max ii device should send the configuration data on the data0 pin one bit at a time. if you are using configuration data in rbf, hex, or ttf format, send the least significant bit (lsb) of ea ch data byte first. for example, if the rbf contains the byte sequence 02 1b ee 01 fa, you should transmit the serial bitstream 0100-0000 1101-1000 0111-0111 1000-0000 0101-1111 to the device first. the cyclone ii device receives configuration data on its data0 pin and the clock on the dclk pin. data is latched into the fpga on the rising edge of dclk . data is continuously clocked into the target device until the conf_done pin transitions high. after the cyclone ii device receives all the configuration data successfully, it releases the open-drain conf_done pin, which is pulled hi gh by an external 10-k pull-up resistor. a low-to-h igh transition on conf_done indicates configuration is complete and initialization of the device can begin. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. the configuration clock ( dclk ) speed must be below the specified system frequency (see table 13?7 ) to ensure correct configuration. no maximum dclk period exists, which means you ca n pause configuration by halting dclk for an indefinite amount of time. initialization stage in cyclone ii devices, the initiali zation clock source is either the cyclone ii internal osc illator (typically 10 mhz) or the optional clkusr pin. the internal oscillator is the default clock source for initialization. if you use the internal oscillator, th e cyclone ii device makes sure to provide enough clock cycles for proper initialization. therefore, if the internal oscillator is the initializat ion clock source, sending the entire configuration file to the device is su fficient to configure and initialize the device. you do not need to provide ad ditional clock cy cles externally during the initialization stage. driving dclk back to the device after configuration is complete does not affect device operation. additionally, if you use the internal oscillator as the clock source, you can use the clkusr pin as a user i/o pin. if you want to delay the initialization of the device, you can use the clkusr pin. using the clkusr pin allows you to control when your device enters user mode. you can delay the device from entering user mode for an indefinite amount of time.
altera corporation 13?25 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices the enable user-supplied start-up clock (clkusr) option can be turned on in the quartus ii software from the general tab of the device & pin options dialog box. suppl ying a clock on clkusr does not affect the configuration process. after all co nfiguration data has been accepted and conf_done goes high, cyclone ii device s require 299 clock cycles to initialize properly and support a clkusr f max of 100 mhz. 1 if the optional clkusr pin is being used and nconfig is pulled low to restart configuration duri ng device initialization, you need to ensure that clkusr continues toggling during the time nstatus is low (maximum of 40 s). an optional init_done pin signals the end of initialization and the start of user mode with a low-to-hig h transition. by default, the init_done output is disabled. you can enable the init_done output by turning on the enable init_done output option in the quartus ii software. if you use the init_done pin, an external 10-k pull-up resistor pulls the pin high when nconfig is low and during the beginning of configuration. once the optional bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin transitions low. when initialization is complete, the init_done pin is released and pulled high. the max ii de vice must be able to detect this low-to-high transition, which signal s the fpga has entered user mode. if you want to use the init_done pin as a user i/o pi n, you should wait for the maximum value of t cd2um (see table 13?7 ) after the conf_done signal transitions high so to ensure the cyclone ii device has been initialized properly and is in user mode. make sure the max ii device does not drive the conf_done signal low during configuration, initialization, and before the device enters user mode. user mode when initialization is complete, the cyclone ii device enters user mode. in user mode, the user i/o pins no longer have pull-up resistors and function as assigned in your design. to ensure dclk and data0 are not left floating at the end of configuration, the max ii device must drive them either high or low, which ever is convenient on yo ur pcb. the cyclone ii device data0 pin is not available as a user i/o pin after configuration. when the fpga is in user mode, you can initiate a reconfiguration by transitioning the nconfig pin low-to-high. the nconfig pin must be low for at least 2 s. when the nconfig transitions low, the cyclone ii
13?26 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration device also pulls nstatus and conf_done low and tri-states all i/o pins. once the nconfig pin returns to a logic high level and the cyclone ii device releases the nstatus pin, the max ii device can begin reconfiguration. error during configuration if an error occurs during configurat ion, the cyclone ii device transitions its nstatus pin low, resetting itself internally. the low signal on the nstatus pin tells the max ii device that th ere is an error. if you turn on the auto-restart configuration after error option in the quartus ii software, the cyclone ii device releases nstatus after a reset time-out period (maximum of 40 s). after nstatus is released and pulled high by a pull-up resistor, the max ii device can try to reconfigure the target device without needing to pulse nconfig low. if this option is turned off, the max ii device must generate a low-to-high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. the max ii device can also monitor the conf_done and init_done pins to ensure successful configuration. the max ii device must monitor the cyclone ii device's conf_done pin to detect errors and determine when programming completes. if all configuration data is sent, but conf_done or init_done do not transition high, the max ii device must reconfigure the target device. f for more information on co nfiguration issues, see the debugging configuration problems chapter of the configuration handbook and the fpga configuration troubleshooter on the altera web site ( www.altera.com ). multiple device ps configuratio n using a max ii device as an external host figure 13?10 shows how to configure multiple devices using a max ii device. this circuit is similar to the ps configuration circuit for a single device, except cyclone ii devices are cascaded for multiple device configuration.
altera corporation 13?27 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices figure 13?10. multiple device ps conf iguration using an external host notes to figure 13?10 : (1) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on the devices and the external host. (2) connect the pull-up resistor to the v ccio supply voltage of i/o bank that the nceo pin resides in. (3) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed another device?s nce pin. in multiple device ps configuration, connect the first cyclone ii device?s nce pin to gnd and connect the nceo pin to the nce pin of the next cyclone ii device in the ch ain. use an external 10-k pull-up resistor to pull the cyclone ii device?s nceo pin high to its v ccio level to help the internal weak pull-up resistor when the nceo pin feeds next cyclone ii device's nce pin. the input to the nce pin of the last cyclone ii device in the chain comes from the previous cyclone ii device. after the first device completes configuration in a multiple device configuration chain, its nceo pin transitions low to activate the second device?s nce pin, which prompts the second device to begin configuration. the second device in the chain begins config uration within one clock cycle. therefore, the max ii device begins to transfer data to the next cyclone ii device without interruption. the nceo pin is a dual-purpose pin in cyclone ii devices. you can leave the nceo pin of the last device unconnected or use it as a user i/o pin after configuration if the last device in chain is a cyclone ii device. 1 the quartus ii software sets the cyclone ii device nceo pin as a dedicated output by default. if the nceo pin feeds the next device?s nce pin, you must make sure that the nceo pin is not used as a user i/o after configuration. this software setting is in the dual-purpose pins tab of the device & pin options dialog box in quartus ii software. external host (max ii device or microprocessor) conf_done nstatus nce data 0 nconfig cyclone ii device 1 memory addr data0 gnd msel0 msel1 v cc (1) v cc (1) 10 k 10 k gnd dclk conf_done nstatus nce data0 nconfig msel0 msel1 gnd dclk nceo nceo n.c. (3) v cc (2) 10 k cyclone ii device 2 v cc v cc
13?28 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration you must connect all othe r configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) to every cyclone ii device in the chain. the configuration signals may require buffering to ensure signal integrity and prevent clock skew proble ms. you should buffer the dclk and data lines for every fourth device. because all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. since all nstatus and conf_done pins are connected, if any cyclone ii device detects an error, configuratio n stops for the entire chain and the entire chain must be reconfigured. fo r example, if th e first cyclone ii detects an error, it resets the chain by pulling its nstatus pin low. this behavior is similar to a single cyclone ii device detecting an error. if the auto-restart config uration after error option is turned on, the cyclone ii devices release their nstatus pins after a reset time-out period (maximum of 40 s). after all nstatus pins are released and pulled high, the max ii device reco nfigures the chai n without pulsing nconfig low. if the auto-restart config uration after error option is turned off, the max ii device must generate a low-to-high transition (with a low pulse of at least 2 s) on nconfig to restart the configuration process. if you want to delay the initialization of the devices in the chain, you can use the clkusr pin option. the clkusr pin allows you to control when your device enters user mode. this feature also allows you to control the order of when each device enters user mode by feeding a separate clock to each device?s clkusr pin. by using the clkusr pins, you can choose any device in the multiple device chain to enter user mode first and have the other devices enter user mode at a later time. different device families may require a different number of initialization clock cycles. therefore, if your multi ple device chain consists of devices from different families, the devices may enter user mode at a slightly different time due to the different n umber of initialization clock cycles required. however, if the number of initialization clock cycles is similar across different device families or if the devices are from the same family, then the devices enter user mode at the same time. see the respective device family handbook for more information about the number of initialization clock cycles required.
altera corporation 13?29 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices if your system has multiple cyclone ii devices (in the same density and package) with the same configuration data, you can configure them in one configuration cycle by connecting all device?s nce pins to ground and connecting all the cyclone ii de vice?s configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) together. you can also use the nceo pin as a user i/o pin after config uration. the configuration signals may require buffering to ensure signal integrity and prevent clock skew problems. make sure the dclk and data lines are buffered for every fourth device. all devices start and complete configuration at the same time. figure 13?11 shows multiple device ps configuration when both cyclone ii devices are receiving the same configuration data. figure 13?11. multiple device ps configuration when both fp gas receive the same data notes to figure 13?11 : (1) the pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the chain. v cc should be high enough to meet the v ih specification of the i/o on the devices and the external host. (2) the nceo pins of both devices can be left unconnected or used as user i/o pins wh en configuring the same configuration data into multiple devices. you can use a single configuration ch ain to configure cyclone ii devices with other altera device s. connect all the cycl one ii device?s and all other altera device?s conf_done and nstatus pins together so all devices in the chain complete configur ation at the same time or that an error reported by one device initiates reconfiguration in all devices. f for more information on configuring multiple altera devices in the same configuration chain, see configuring mixed al tera fpga chains in the configuration handbook . external host (max ii device or microprocessor) conf_done nstatus nce data 0 nconfig cyclone ii device memory addr data0 gnd msel0 msel1 v cc (1) v cc (1) 10 k 10 k gnd dclk conf_done nstatus nce data0 nconfig msel0 msel1 gnd dclk nceo n.c. (2) cyclone ii device nceo n.c. (3) gnd v cc v cc
13?30 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration ps configuration timing a ps configuration must meet the setup and hold timing parameters and the maximum clock frequency. when using a microprocessor or another intelligent host to control the ps inte rface, ensure that you meet these timing requirements. figure 13?12 shows the timing waveform for ps configuration for cyclone ii devices. figure 13?12. ps configuration timing waveform note (1) notes to figure 13?12 : (1) the beginning of this waveform shows the device in user mode. in user mode, nconfig , nstatus and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) upon power-up, the cyclone ii device holds nstatus low for the time of the por delay. (3) upon power-up, before and during configuration, conf_done is low. (4) in user mode, drive dclk either high or low when using the ps configuration scheme, whichever is more convenient. when using the as configuration scheme, dclk is a cyclone ii output pin and should not be driven externally. (5) do not leave the data pin floating after configurat ion. drive it high or low, whichever is more convenient. nconfig nstatus (2) conf_done (3) dclk (4) data user i/o init_done bit 0 bit 1 bit 2 bit 3 bit n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck user mode (5) tri-stated with internal pull-up resistor
altera corporation 13?31 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices table 13?7 defines the timing parameters for cyclone ii devices for ps configuration. f device configuration options and how to create configuration files are discussed further in the software settings section in volume 2 of the configuration handbook . ps configuration using a microprocessor in the ps configuration scheme, a micr oprocessor can control the transfer of configuration data from a storage device, such as flash memory, to the target cyclone ii device. table 13?7. ps timing parameters for cyclone ii devices symbol parameter minimum maximum units t por por delay (1) 100 ms t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns t cfg nconfig low pulse width 2 s t status nstatus low pulse width 10 40 (2) s t cf2st1 nconfig high to nstatus high 40 (2) s t cf2ck nconfig high to first rising edge on dclk 40 s t st2ck nstatus high to first rising edge on dclk 1 s t dsu data setup time before rising edge on dclk 7 ns t dh data hold time after rising edge on dclk 0 ns t ch dclk high time 4 ns t cl dclk low time 4 ns t clk dclk period 10 ns f max dclk frequency 100 mhz t cd2um conf_done high to user mode (3) 18 40 s t cd2cu conf_done high to clkusr enabled 4 maximum dclk period t cd2umc conf_done high to user mode with clkusr option on t cd2cu + (299 clkusr period) notes to table 13?7 : (1) the por delay minimum of 100 ms only applies for non ?a? devices. (2) this value is applicable if users do not delay configuration by extending the nconfig or nstatus low pulse width. (3) the minimum and maximum numbers apply on ly if the internal oscillator is chosen as the clock source for starting the device.
13?32 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration f all information in the ?single device ps configuration using a max ii device as an external host? on page 13?22 section is also applicable when using a microprocessor as an ex ternal host. refer to that section for all configuration information. the microblaster? software driver allows you to configure altera fpgas, including cyclone ii devices, through the byteblaster ii or byteblastermv cable in ps mode. the microblaster software driver supports a rbf programming input file and is targeted for embedded ps configuration. the source code is developed for the windows nt operating system, although you can customize it to run on other operating systems. 1 since the cyclone ii device can decompress the compressed configuration data on-the-fly during ps configuration, the microblaster software can accept a compressed rbf file as its input file. f for more information on the microblaster software driver, see the configuring the microblaster passive serial software driver white paper and source files on the altera web site at www.altera.com . if you turn on the enable user-supplied start-up clock (clkusr) option in the quartus ii software, the cycl one ii devices does not enter user mode after the microblaster has transmitted all the configuration data in the rbf file. you need to supply enou gh initialization clock cycles to clkusr pin to enter user mode. single device ps configuratio n using a configuration device you can use an altera configuration de vice (for example, an epc2, epc1, or enhanced configuration device) to configure cyclone ii devices using a serial configuration bitstream. co nfiguration data is stored in the configuration device. figure 13?13 shows the configuration interface connections between the cyclone ii de vice and a configuration device. 1 the figures in this chapter only show the configuration-related pins and the configuration pin connections between the configuration device and the fpga. f for more information on enhanced configuration devices and flash interface pins (e.g., pgm[2..0] , exclk , porsel , a[20..0] , and dq[15..0] ), see the enhanced configuration devices (epc4, epc8 & epc16) data sheet .
altera corporation 13?33 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices figure 13?13. single device ps configuration using an enhanced configuration device notes to figure 13?13 : (1) the pull-up resistor sh ould be connected to the same supply voltage as the configuration device. this pull-up resistor is 10 k . (2) the ninit_conf pin is available on enhanced configuration devices and has an internal pull-up resistor that is always active, meaning an external pull-up resistor should not be used on the ninit_conf to nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or th rough a resistor (if reconfiguration is required , a resistor is necessary). (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if intern al pull-up resistors are used, external pull-up resistors should not be used on th ese pins. the internal pull-up resistors are used by default in the quartus ii soft ware. to turn off the internal pull-up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. (4) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed other device?s nce pin. f the value of the internal pull-up resi stors on the enhanced configuration devices and epc2 devices can be found in the enhanced configuration devices (epc4, epc8, & epc16) data sheet or the configuration devices for sram-based lut devices data sheet . when using enhanced configuration devices or epc2 devices, you can connect the cyclone ii nconfig pin to the configuration device ninit_conf pin, which allows the init_conf jtag instruction to initiate fpga configuration. you do not need to connect the ninit_conf pin if you are not using it. if ninit_conf is not used or not available (e.g., on epc1 devices), pull the nconfig signal to v cc either directly or through a resistor (if reconfiguration is required, a resistor is necessary). an internal pull-up resistor on the ninit_conf pin is always active in enhanced configuration de vices and epc2 devices. therefore, you do not need an external pull-up if nconfig is connected to ninit_conf . cyclone ii fpga dclk data oe ncs ninit_conf (2) msel0 msel1 dclk data0 nstatus conf_done nconfig v cc v cc gnd (1) (1) nce nceo n.c. (4) (3) (3) enhanced configuration device 10 k 10 k 10 k v cc v cc (1) gnd
13?34 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration upon power-up, the cyclone ii device goes through a por. during por, the device reset, holds nstatus and conf_done low, and tri-states all user i/o pins. after por, which ty pically lasts 100 ms, the cyclone ii fpga releases nstatus and enters configuration mode when this signal is pulled high by the external 10-k resistor. once the fpga successfully exits por, all user i/o pins continue to be tri-stated. cyclone ii devices have weak pull-up resistors on the us er i/o pins which are on before and during configuration. the configuration device also goes through a por delay to allow the power supply to stabilize. the maximu m por time for epc2 or epc1 devices is 200 ms. the por time for enhanced configur ation devices can be set to 100 ms or 2 ms, depending on the enhanced configuration device?s porsel pin setting. if the porsel pin is connected to ground, the por delay is 100 ms. if the porsel pin is connected to v cc , the por delay is 2 ms. you must power the cyclone ii device before or during the enhanced configuration device por ti me. during por, the configuration device transitions its oe pin low. this low signal delays configuration because the oe pin is connected to the target device?s nstatus pin. when the target and configuration devices co mplete por, they both release the nstatus to oe line, which is then pulled high by a pull-up resistor. when the power supplies have reached the appropriate operating voltages, the target fpga senses the low-to-high transition on nconfig and initiates the configuration cycle. the configuration cycle consists of three stages: reset, configuration, and initialization. 1 the cyclone ii device does not have a porsel pin. reset stage while nconfig or nstatus is low, the device is in reset. you can delay configuration by holding the nconfig or nstatus pin low. 1 v ccint and v ccio of the banks where the configuration and jtag pins reside need to be fully powered to the appropriate voltage levels in order to begin the configuration process. when the nconfig signal goes high, the devi ce comes out of reset and releases the nstatus pin, which is pulled hi gh by a pull-up resistor. enhanced configuration and epc2 devices have an optional internal pull-up resistor on the oe pin. you can turn on this option in the quartus ii software from the general tab of the device & pin options dialog box. if this internal pull-u p resistor is not used, you need to connect an external 10-k pull-up resistor to the oe and nstatus line. once nstatus is released, the fpga is ready to receive configuration data and the configuration stage begins.
altera corporation 13?35 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices configuration stage when the nstatus pin transitions high, th e configuration device?s oe pin also transitions high and the co nfiguration device clocks data out serially to the fpga us ing its internal oscillator. the cyclone ii device receives configuration data on its data0 pin and the clock is received on the dclk pin. data is latched into the fpga on the rising edge of dclk . after the fpga has received all configuration data successfully, it releases the open-drain conf_done pin, which is pulled high by a pull- up resistor. since th e cyclone ii device?s conf_done pin is tied to the configuration device's ncs pin, the configuration device is disabled when conf_done goes high. enhanced configuration and epc2 devices have an optional internal pull-up resistor on the ncs pin. you can turn this option on in the quartu s ii software from the general tab of the device & pin options dialog box. if you do not use this internal pull-up resistor, you need to connect an external 10-k pull-up resistor to the ncs and conf_done line. a low-to-high transition on conf_done indicates configuration is complete, and the device can begin initialization. initialization stage in cyclone ii devices, the default initialization clock source is the cyclone ii internal oscill ator (typically 10 mhz). cyclone ii devices can also use the optional clkusr pin. if your design uses the internal oscillator, the cyclone ii device supplie s itself with enou gh clock cycles for proper initialization. the advantage of using the internal oscillator is you do not need to use another device or source to send additional clock cycles to the clkusr pin during the initialization stage. additionally, you can use of the clkusr pin as a user i/o pin, which means you have an additional user i/o pin. if you want to delay the initialization of the device, you can use the clkusr pin. using the clkusr pin allows you to control when the cyclone ii device enters user mode. you can delay the cyclone ii devices from entering user mode for an inde finite amount of time. you can turn on the enable user-supplied start-up clock (clkusr) option in the quartus ii software from the general tab of the device & pin options dialog box. suppl ying a clock on clkusr does not affect the configuration process. after all configuration data is accepted and conf_done goes high, cyclone ii devices require 299 clock cycles to properly initialize and support a clkusr f max of 100 mhz. an optional init_done pin is available, which signals the end of initialization and the start of user mo de with a low-to-hi gh transition. the enable init_done output option is available in the quartus ii software from the general tab of the device & pin options dialog box. if you use the init_done pin, an external 10-k pull-up resistor pulls it high when
13?36 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration nconfig is low and during the beginning of configuration. once the optional bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the init_done pin is released and pulled high. this low-to-high transition signals th at the fpga has entered user mode. if you do not use the init_done pin, the initialization period is complete after the conf_done signal transitions high an d 299 clock cycles are sent to the clkusr pin or after the time t cf2um (see table 13?7 ) if the cyclone ii device uses th e internal oscillator. after successful configuration, if you intend to synchronize the initialization of multiple devices that are not in the same configuration chain, your system must not pull the conf_done signal low to delay initialization. instead, use the optional clkusr pin to synchronize the initialization of multiple devices that are not in the same configuration chain. devices in the same configuration chain initialize together if their conf_done pins are tied together. 1 if the optional clkusr pin is being used and nconfig is pulled low to restart configuration duri ng device initialization, you need to ensure that clkusr continues toggling during the time nstatus is low (maximum of 40 s). user mode when initialization is complete, the fpga enters user mode. in user mode, the user i/o pins do not have weak pull-up resistors and function as assigned in your design. enhanced configuration devices and epc2 devices drive dclk low and data0 high (epc1 devices drive the dclk pin low and tri-state the data pin) at the end of configuration. when the fpga is in user mode, pull the nconfig pin low to begin reconfiguration. the nconfig pin should be low for at least 2 s. when nconfig transitions low, the cyclon e ii device also pulls the nstatus and conf_done pins low and all i/o pins are tri-stated. because conf_done transitions low, this activate s the configuration device since it will see its ncs pin transition low. once nconfig returns to a logic high level and nstatus is released by the fpga, reconfiguration begins. error during configuration if an error occurs during config uration, the cyclone ii drives its nstatus pin low, resetting itself internally. since the nstatus pin is tied to oe, the configuration device is also reset. if you turn on the auto-restart configuration after error option in the quartus ii software from the general tab of the device & pin options dialog box, the fpga automatically initiates reconfiguration if an error occurs. the cyclone ii
altera corporation 13?37 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices device releases its nstatus pin after a reset time -out period (maximum of 40 s). when the nstatus pin is released and pu lled high by a pull-up resistor, the configuration device reconf igures the chain. if this option is turned off, the external system must monitor nstatus for errors and then pulse nconfig low for at least 2 s to restart configuration. the external system can pulse the nconfig pin if the pin is under system control rather than tied to v cc . additionally, if the configuration device sends all of its data and then detects that the conf_done pin has not transitioned high, it recognizes that the fpga has not configured su ccessfully. enhanc ed configuration devices wait for 64 dclk cycles after the last configuration bit was sent for the conf_done pin to transition high. epc2 devices wait for 16 dclk cycles. after that, the configuration device pulls its oe pin low, which in turn drives the target device?s nstatus pin low. if you turn on the auto- restart configuration after error option in the quartus ii software, the target device resets and then releases its nstatus pin after a reset time- out period (maximum of 40 s). when nstatus transitions high again, the configuration device reconfigures the fpga. f for more information on co nfiguration issues, see the debugging configuration problems chapter of the configuration handbook and the fpga configuration troubleshooter on the altera web site ( www.altera.com ). multiple device ps configuratio n using a configuration device you can use altera enha nced configuration devi ces (epc16, epc8, and epc4 devices) or epc2 and epc1 configuration devices to configure multiple cyclone ii devices in a ps configuration chain. figure 13?14 shows how to configure multip le devices with an enhanced configuration device. this circuit is similar to the configuration device circuit for a single device, except cyclone ii devices are cascaded for multiple device configuration.
13?38 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration figure 13?14. multiple device ps configuration using an e nhanced configuration device notes to figure 13?14 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active, meaning an external pull-up resistor should not be used on the ninit_conf to nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor (if reconfiguration is required, a resistor is necessary). (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. (4) connect the pull-up resistor to the v ccio supply voltage of i/o bank that the nceo pin resides in. (5) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed other device?s nce pin. 1 you cannot cascade enhanced configuration devices (epc16, epc8, and epc4 devices). when configuring multiple devices, you must generate the configuration device's pof from each project's sof. you can combine multiple sofs using the convert programming files window in the quartus ii software. f for more information on how to crea te configuration files for multiple device configuration chains, see the software settings section in volume 2 of the configuration handbook . when configuring multiple devices with the ps scheme, connect the first cyclone ii device?s nce pin to gnd and connect its nceo pin to the nce pin of the cyclone ii device in the chain. use an external 10-k pull-up resistor to pull the cyclone ii device?s nceo pin to the v ccio level when enhanced configuration device dclk data oe ncs ninit_conf (2) dclk data0 nstatus conf_done nconfig v cc v cc gnd nce msel0 msel1 dclk data0 nstatus conf_done nconfig gnd nce msel0 msel1 nceo cyclone ii device 1 (1) v cc (1) (3) nceo cyclone ii device 2 (3) n.c. 10 k v cc (4) (5) 10 k 10 k (3) (3) gnd v cc
altera corporation 13?39 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices it feeds the next device?s nce pin. after the first device in the chain completes configuration, its nceo pin transitions low to activate the second device's nce pin, which prompts the second device to begin configuration. you can leave the nceo pin of the last device unconnected or use it as a user i/o pin after configuration. the nceo pin is a dual-purpose pin in cyclone ii devices. 1 the quartus ii software sets the cyclone ii device nceo pin as an output pin driving to ground by default. if the device is in a chain, and the nceo pin is connected to the next device?s nce pin, you must make sure that the nceo pin is not used as a user i/o pin after configuration. this software setting is in the dual-purpose pins tab of the device & pin options dialog box in quartus ii software. connect all other configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) to every cyclone ii device in the chain. the configuration signals may require buffering to ensure signal integrity and prevent clock skew problems. buffer the dclk and data lines for every fourth device. when configuring multiple devices, co nfiguration does not begin until all devices release their oe or nstatus pins. similarly, since all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. you should not pull conf_done low to delay initialization. instead, use the quartus ii software?s user-supplied start-up clock option to synchronize the initialization of multipl e devices that are not in the same configuration chain. devices in the same configuration chain initialize together since their conf_done pins are tied together. since all nstatus and conf_done pins are connected, if any device detects an error, configuration stops for the entire chain and the entire chain must be reconfigured. for example, if there is an error when configuring the first cyclone ii device, it resets the chain by pulling its nstatus pin low. this low signal drives the oe pin low on the enhanced configuration device and drives nstatus low on all fpgas, which causes them to enter a reset state. if the auto-restart config uration after error option is turned on, the devices automatically initiate reconfiguration if an error occurs. the fpgas release their nstatus pins after a reset time-out period (40 s maximum). when all the nstatus pins are released and pulled high, the configuration device reconfigures the chain. if the auto-restart configuration after error option is turned off, a microprocessor or controller must monitor the nstatus pin for errors and then pulse
13?40 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration nconfig low for at least 2 s to restart configuration. the microprocessor or controller can only transition the nconfig pin low if the pin is under system control and not tied to v cc . the enhanced configuration devices su pport parallel configuration of up to eight devices. the n -bit ( n = 1, 2, 4, or 8) ps configuration mode allows enhanced configuration devices to concurrently configure a chain of fpgas. these devices do not have to be the same device family or density; they can be any combinatio n of altera fpgas with different designs. an individual enhanced configuration device data pin is available for each targeted fpga. each data line can also feed a chain of fpgas. figure 13?15 shows how to concurrently configure multiple devices using an enhanced configuration device.
altera corporation 13?41 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices figure 13?15. concurrent ps configuration of multi ple devices using an enhanc ed configuration device notes to table 13?15 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active, meaning an external pull-up resistor should not be used on the ninit_conf to nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor (if reconfiguration is required, a resistor is necessary). (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. (4) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed other device?s nce pin. the quartus ii software only allows you to set n to 1, 2, 4, or 8. however, you can use these modes to configure an y number of devices from 1 to 8. for example, if you configure three fpgas, you would use the 4-bit ps mode. for the data0 , data1 , and data2 lines, the corresponding sof data is transmitted from the configuration device to the fpga. for msel1 msel0 dclk data0 nstatus conf_done nconfig v cc gnd (3) (4) nce (3) cyclone ii device 1 v cc msel1 msel0 dclk data0 nconfig nce msel1 msel0 dclk data 0 gnd gnd dclk data0 oe (3) ncs (3) ninit_conf (2) data 1 data[2..6] nstatus conf_done nstatus conf_done nconfig nce data 7 10 k 10 k cyclone ii device 2 cyclone ii device 8 n.c. nceo n.c. nceo n.c. nceo (1) (1) enhanced configuration device gnd v cc gnd v cc gnd v cc (4) (4)
13?42 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration data3 , you can leave the corresponding bit 3 line blank in the quartus ii software. on the printed circ uit board (pcb), leave the data3 line from the enhanced configuration device unconnected. use the quartus ii convert programming files window (tools menu) setup for this scheme. you can also connect two fpgas to one of the configuration device?s data pins while the other data pins drive one device each. for example, you could use the 2-bit ps mode to drive two fpgas with data bit 0 (two ep2c5 devices) and the third device (an ep2c8 device) with data bit 1. in this example, the memory space required for data bit 0 is the sum of the sof file size for the two ep2c5 devices. 1,223,980 bits + 1,223,980 bits = 2,447,960 bits the memory space required for data bit 1 is the sof file size for on ep2c8 device (1,983,792 bits). sinc e the memory space required for data bit 0 is larger than the memory space required for data bit 1, the size of the pof file is 2 2,447,960 = 4,895,920. f for more information on using n -bit ps modes with enhanced configuration devices, see the using altera enhanced configuration devices in the configuration handbook . when configuring sram-based devices using n -bit ps modes, use table 13?8 to select the appropriate configuration mode for the fastest configuration times. table 13?8. recommended configurat ion using n-bit ps modes number of devices (1) recommended configuration mode 11-bit ps 22-bit ps 34-bit ps 44-bit ps 58-bit ps 68-bit ps 78-bit ps 88-bit ps note to table 13?8 : (1) assume that each data line is only configuring on e device, not a daisy chain of devices.
altera corporation 13?43 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices if your design has multiple cyclon e ii devices of the same density and package that contain the same configuration data, connect the nce inputs to gnd and leave the nceo pins floating. you can also use the nceo pin as a user i/o pin. connect the configuration device nconfig , nstatus , dclk , data0 , and conf_done pins to each cyclone ii device in the chain. the configuration signals may require buffering to ensure signal integrity and prevent clock skew problems. make sure that the dclk and data lines are buffered for every fourth device. all devices start and complete configuratio n at the same time. figure 13?16 shows multiple device ps configuration when the cyclone ii devices are receiving the same configuration data.
13?44 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration figure 13?16. multiple device ps c onfiguration using an enhanced c onfiguration device when fpgas receive the same data notes to figure 13?16 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin is available on enhanced configuration devi ces and has an internal pull-up resistor that is always active, meaning an external pull-up resistor should not be used on the ninit_conf to nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor (if reconfiguration is required, a resistor is necessary). (3) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. (4) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed other device?s nce pin. you can cascade several epc2 or ep c1 devices to configure multiple cyclone ii devices. the first configuration device in the chain is the master configuration device, and the subsequent devices are the slave devices. the master configuration device sends dclk to the cyclone ii msel1 msel0 dclk data0 nconfig v cc gnd (3) nce (3) v cc msel1 msel0 dclk data 0 nstatus conf_done nconfig nce nstatus conf_done msel1 msel0 dclk data0 nconfig nce gnd gnd cyclone ii device 1 cyclone ii device 2 cyclone ii device 8 dclk data 0 oe ncs ninit_conf (2) nstatus conf_done n.c. nceo n.c. nceo n.c. nceo (4) (4) (4) (1) (1) 10 k 10 k (3) (3) enhanced configuration device gnd v cc gnd v cc gnd v cc
altera corporation 13?45 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices devices and to the slave configur ation devices. connect the first configuration device?s ncs pin to all the cyclone ii device?s conf_done pins, and connect the ncasc pin to the ncs pin of the next configuration device in the chain. leave the ncasc pin of the last configuration device floating. when the master configurat ion device sends all the data to the cyclone ii device, the configur ation device transitions the ncasc pin low, which drives ncs on the next configuration device. because a configuration device requires less than one clock cycle to activate a subsequent configuration device, the data stream is uninterrupted. 1 enhanced configuration devices (epc16, epc8, and epc4 devices) cannot be cascaded. since all nstatus and conf_done pins are connected, if any device detects an error, the master configur ation device stops configuration for the entire chain and the entire chain must be reconfigured. for example, if the master configuration device does not detect the cyclone ii device?s conf_done pin transitioning high at the en d of configuration, it resets the entire chain by transitioning its oe pin low. this low signal drives the oe pin low on the slave configuration device(s) and drives nstatus low on all cyclone ii devices, causing them to enter a reset state. this behavior is similar to the fpga dete cting an error in the configuration data. figure 13?17 shows how to configure multiple devices using cascaded epc2 or epc1 devices.
13?46 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration figure 13?17. multiple device ps configuration using cascaded epc2 or epc1 devices notes to figure 13?17 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) the ninit_conf pin (available on enhanced conf iguration devices and epc2 device s only) has an internal pull-up resistor that is always active, meaning an extern al pull-up resistor should not be used on the ninit_conf to nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used or not available (e.g., on epc1 devices), nconfig must be pulled to v cc either directly or through a resistor (if reconfiguration is re quired, a resistor is necessary). (3) the enhanced configuration devices? and epc2 devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-u p resistors are used, external pull-up resistors should not be used on these pins. the internal pull-up resistors are used by default in the quartu s ii software. to turn off the internal pull-up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. (4) use an external 10-k pull-up resistor to pull the nceo pin high to the i/o bank v ccio level to help the internal weak pull-up when it feeds next device?s nce pin. (5) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed other device?s nce pin. when using enhanced configuration devices or epc2 devices, you can connect the cyclone ii device?s nconfig pin to the configuration device?s ninit_conf pin, which allows the init_conf jtag instruction to initiate fpga configuration. you do not need to connect the ninit_conf pin if it is not used. if the ninit_conf pin is not used or not available (for example, on epc1 devices), pull the nconfig pin to v cc levels either directly or throug h a resistor (if reconfiguration is required, a resistor is necessary). an internal pull-up resistor on the ninit_conf pin is always active in the enhanced configuration devices and the epc2 devices. therefore, do not use an external pull-up resistor if you connect the nconfig pin to ninit_conf . if you use multiple epc2 devices to configure a cyclone ii device(s), only connect the first epc2 device?s ninit_conf pin to the device's nconfig pin. epc2 or epc1 device 1 dclk data oe ncs ninit_conf (2) dclk data0 nstatus conf_done nconfig gnd nce v cc v cc v cc dclk data ncs oe msel0 msel1 dclk data0 nstatus conf_done nconfig gnd nce msel0 msel1 nceo (2) ncasc cyclone ii device 1 (1) v cc (1) (1) (3) (5) nceo ninit_conf cyclone ii device 2 (3) n.c. epc2 or epc1 device 2 10 k 10 k 10 k (3) (3) gnd v cc (4) v cc 10 k
altera corporation 13?47 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices you can use a single configuration ch ain to configure cyclone ii devices with other altera devices. to ensure that all devices in the chain complete configuration at the same time or that an error flagged by one device initiates reconfiguration in all devices, connect all the cyclone ii device conf_done pins and connect all cyclone ii device nstatus pins together. f for more information on configuring multiple altera devices in the same configuration chain, see the configuring mixed altera fpga chains chapter in the configuration handbook . during ps configuration, the design must meet the setup and hold timing parameters and maximum dclk frequency. the enhanced configuration and epc2 devices are designed to meet these interface timing specifications. figure 13?18 shows the timing waveform fo r the ps config uration scheme using a configuration device. figure 13?18. cyclone ii ps configuration using a configuration device timing waveform note to figure 13?18 : (1) cyclone ii devices enter user mode 299 clock cycles after conf_done goes high. the initialization clock can come from the cyclone ii intern al oscillator or the clkusr pin. f for timing information, refer to the enhanced configuration devices (epc4, epc8, and epc16) data sheet or the configuration devices for sram-based lut devices data sheet in the configuration handbook . f for more information on device configuration options and how to create configuration files, see the software settings section in volume 2 of the configuration handbook . dd d d 0 1 2 3 d n user mode t cd2um (1) t oezx t por t ch t cl t dsu t co t dh tri-stated with internal pull-up resistor oe/nstatus ncs/conf_done dclk data user i/o init_done ninit_conf or vcc/nconfig
13?48 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration ps configuration using a download cable in ps configuration, an intelligent host (e.g., a pc) can use a download cable to transfer data from a storag e device to the cyclone ii device. you can use the altera usb-blaster univer sal serial bus (usb) port download cable, masterblaster? serial/usb co mmunications cable, byteblaster ii parallel port download cable, or th e byteblastermv? parallel port as a download cable. upon power up, the cyclone ii device goes through por, which lasts approximately 100 ms for non ?a? de vices. during por, the device resets, holds nstatus low, and tri-states all user i/o pins. once the fpga successfully exits por, the nstatus pin is released and all user i/o pins continue to be tri-stated. f the value of the weak pull-up resis tors on the i/o pins that are on before and during configuration can be found in the cyclone ii device handbook . the configuration cycle consists of three stages: reset, configuration, and initialization. while the nconfig or nstatus pins are low, the device is in reset. to initiate configuration in this scheme, the download cable generates a low-to-high transition on the nconfig pin. 1 make sure v ccint and v ccio for the banks where the configuration and jtag pins reside are powered to the appropriate voltage levels in order to begin the configuration process. when nconfig transitions high, the cyclone i i device comes out of reset and begins configuration. the cyclon e ii device releases the open-drain nstatus pin, which is then pulled high by an external 10-k pull-up resistor. once nstatus transitions high, the cyclone ii device is ready to receive configuration data. the programming hardware or download cable then transmits the configuration data one bit at a time to the device?s data0 pin. the configuration data is clocked into the target device until conf_done goes high. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. when using a download cable, you cannot use the auto-restart configuration after error option. you must manually restart configuration in the quartus ii software when an error occurs. additionally, you cannot use the enable user-supplied start-up clock (clkusr) option when programming th e fpga using the quartus ii programmer and download cable. this option is disabled in the sof. therefore, if you turn on the clkusr option, you do not need to provide a clock on clkusr when you are configuring the fpga with the
altera corporation 13?49 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices quartus ii programmer and a download cable. figure 13?19 shows the ps configuration for cyclone ii devices using a usb-blaster, masterblaster, byteblaster ii or byteblastermv cable. figure 13?19. ps configuration using a usb-blaster, mast erblaster, byteblaster ii or byteblastermv cable notes to figure 13?19 : (1) the pull-up resistor should be connected to the sa me supply voltage as the usb-blaster, masterblaster ( vio pin), byteblaster ii, or byteblastermv cable. (2) the pull-up resistors on data0 and dclk are only needed if the download ca ble is the only configuration scheme used on your board. this is to ensure that data0 and dclk are not left floating after co nfiguration. for example, if you are also using a configuration device, the pull-up resistors on data0 and dclk are not needed. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable data sheet for this value. in the byteblastermv, this pin is a no connect. in the usb-blaster and byteblaster ii, this pin is connected to nce when it is used for as programming, otherwise it is a no connect. (4) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed other device?s nce pin. you can use a download cable to configure multiple cyclone ii devices by connecting each device?s nceo pin to the subseq uent device?s nce pin. connect the first cyclone ii device?s nce pin to gnd and connect its nceo pin to the nce pin of the next device in the chain. use an external 10-k pull-up resistor to pull the nceo pin high to v ccio when it feeds next device?s nce pin. connect all other configuration pins ( nconfig , nstatus , dclk , data0 , and conf_done ) on every device in the chain together. because all conf_done pins are connected, all devices in the chain initialize and enter user mode at the same time. usb-blaster, byteblaster ii, masterblaster, or byteblastermv 10-pin male header v cc (1) v cc (1) v cc v cc (1) cyclone ii device dclk nconfig conf_done shield gnd msel1 msel0 10 k 10 k 10 k nstatus data0 pin 1 nce gnd gnd vio (3) v cc v cc (1) 10 k (2) v cc (1) 10 k (2) nceo n.c. (4)
13?50 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration in addition, because the nstatus pins are connected, all the cyclone ii devices in the chain stop configuration if any device detects an error. if this happens, you must manually rest art configuration in the quartus ii software. figure 13?20 shows how to configure multiple cyclone ii devices with a download cable.
altera corporation 13?51 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices figure 13?20. multiple device ps confi guration using a usb-blaster, mast erblaster, byteblaster ii or byteblastermv cable notes to figure 13?20 : (1) the pull-up resistor should be connected to the sa me supply voltage as the usb-blaster, masterblaster ( vio pin), byteblaster ii, or byteblastermv cable. (2) the pull-up resistors on data0 and dclk are only needed if the download ca ble is the only configuration scheme used on your board. this is to ensure that data0 and dclk are not left floating after co nfiguration. for example, if you are also using a configuration device, the pull-up resistors on data0 and dclk are not needed. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device's v ccio . refer to the masterblaster serial/usb communic ations cable data sheet for this value. in the byteblastermv, this pin is a no co nnect. in the usb-blaster and byteblaster ii, this pin is connected to nce when it is used for as programming, otherwise it is a no connect. (4) connect the pull-up resistor to the v ccio supply voltage of i/o bank that the nceo pin resides in. (5) the nceo pin of the last device in chain can be le ft unconnected or used as a user i/o pin. if you are using a download cable to configure cyclone ii devices on a pcb that also has configuration devices, you should electrically isolate the configuration devices from the target cyclone ii devices and cable. one way to isolate the configuration device is to add logic, such as a multiplexer, that can select betwee n the configuration device and the cable. the multiplexer should allo w bidirectional transfers on the nstatus and conf_done signals. additionally, you can add switches to cyclone ii fpga 1 cyclone ii fpga 2 msel0 nce nconfig conf_done dclk nce nceo nconfig conf_done dclk nceo gnd (passive serial mode) v cc (2) v cc (1) gnd v cc (1) v cc (1) nstatus nstatus data0 data0 msel1 msel0 msel1 10 k 10 k 10 k pin 1 usb-blaster, byteblaster ii, masterblaster, or byteblastermv 10-pin male header n.c. (5) vio (3) gnd v cc gnd v cc v cc (1) 10 k (2) v cc (1) 10 k (2) v cc (4) 10 k
13?52 altera corporation cyclone ii device handbook, volume 1 february 2007 ps configuration the five common signals ( nconfig , nstatus , dclk , data0 , and conf_done ) between the cable and the configuration device. you can also remove the configuration device from the board when configuring the fpga with the cable. figure 13?21 shows a combination of a configuration device and a download cable to configure an fpga. figure 13?21. ps configuration with a downl oad cable & configuration device circuit notes to figure 13?21 : (1) the pull-up resistor should be connected to the same supply volt age as the configuration device. (2) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable data sheet for this value. in the byteblastermv, this pin is a no connect. in the usb-blaster and byteblaster ii, this pin is connected to nce when it is used for as programming, otherwise it is a no connect. (3) you should not attempt configuration with a download cable while a configuration device is connected to a cyclone ii device. instead, you should either remove the configuration device from its socket when using the download cable or place a switch on the five common signals between the download cable and the configuration device. (4) the ninit_conf pin (available on enhanced conf iguration devices and epc2 device s only) has an internal pull-up resistor that is always active. this means an exte rnal pull-up resistor should not be used on the ninit_conf to nconfig line. the ninit_conf pin does not need to be connected if its functionality is not used. if ninit_conf is not used or not available (e.g., on epc1 devices), nconfig must be pulled to v cc either directly or through a resistor (if reconfiguration is re quired, a resistor is necessary). (5) the enhanced conf iguration devices? oe and ncs pins have internal programmable pull-up resistors. if internal pull-up resistors are used, external pull-up resistors should not be used on these pins. th e internal pull-up resistors are used by default in the quartus ii software. to turn off the internal pull -up resistors, check the disable ncs and oe pull-ups on configuration device option when generating programming files. (6) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed other device?s nce pin. cyclone ii fpga msel0 nce nconfig conf_done dclk nceo gnd usb blaster, byteblaster ii, masterblaster, or byteblastermv 10-pin male header (passive serial mode) v cc v cc v cc (1) v cc (1) nstatus data0 msel1 10 k 10 k 10 k pin 1 dclk data oe (5) ncs (5) ninit_conf (4) configuration device (3) (3) (3) (3) (3) gn d vio (2) n.c. (6) (1) gnd v cc (4) (5) (5)
altera corporation 13?53 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices f for more information on how to use the usb-blaster, masterblaster, byteblaster ii or byteblastermv cabl es, refer to the following documents: usb-blaster usb port download cable data sheet masterblaster serial /usb communication s cable data sheet byteblaster ii parallel port download cable data sheet byteblastermv parallel port download cable data sheet jtag configuration the joint test action group (jtag) has developed a specification for boundary-scan testing. this boundary-s can test (bst) architecture allows you to test components on pcbs with tight lead spacing. the bst architecture can test pin connections without using physical test probes and capture functional data while a device is operating normally. the jtag circuitry can also be used to shift configuration data into the device. the quartus ii software automatically generates sof fi les that can be used for jtag configuration with a download cable in the quartus ii programmer. f for more information on jtag bounda ry-scan testing, see the following documents: ieee 1149.1 (jtag) boun dary-scan testing for cyclone ii devices chapter in volume 2 of the cyclone ii device handbook jam programming & testing language specification cyclone ii devices are designed such that jtag instructions have precedence over any device configur ation modes. this means that jtag configuration can take place withou t waiting for other configuration modes to complete. for example, if you attempt jtag configuration of cyclone ii devices during ps configur ation, ps configur ation terminates and jtag configuration be gins. if the cyclone ii msel pins are set to as or fast as mode, the cyclone ii device does not output a dclk signal when jtag configuration takes place. 1 you cannot use the cyclone ii decompression feature if you are configuring your cyclone ii device when using jtag-based configuration.
13?54 altera corporation cyclone ii device handbook, volume 1 february 2007 jtag configuration a device operating in jtag mode uses the tdi , tdo , tms , and tck pins. the tck pin has a weak intern al pull-down resistor while the other jtag input pins, tdi and tms , have weak internal pull-up resistors. all user i/o pins are tri-stated during jtag configuration. table 13?9 explains each jtag pin's function. 1 the tdo output is powered by the v ccio power supply. if v ccio is tied to 3.3-v, both the i/o pins and the jtag tdo port drive at 3.3-v levels. table 13?9. dedicated jtag pins pin name pin type description tdi test data input serial input pin for instructions as well as test and programming data. data is shifted in on the rising edge of tck . if the jtag interface is not required on the board, the jtag circuitr y can be disabled by connecting this pin to v cc . tdo test data output serial data output pin for instructions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. if the jtag interface is not required on the board, the jtag circuitr y can be disabled by leaving this pin unconnected. tms test mode select input pin that provides the control signal to determine the transitions of the tap controller state machine. transitions within the state machine occur on the rising edge of tck . therefore, tms must be set up before the rising edge of tck . tms is evaluated on the rising edge of tck . if the jtag interface is not required on the board, the jtag circuitr y can be disabled by connecting this pin to v cc . tck test clock input the clock input to the bst circuitry. some operations occur at the rising edge, while others occur at the falling edge. if the jtag interface is not required on the board, the jtag circuitr y can be disabled by connecting this pin to gnd.
altera corporation 13?55 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices single device jtag configuration during jtag configuration, you can use the usb-blaster, masterblaster, byteblaster ii, or byteblastermv down load cable to download data to the device. configuring cyclone ii devices through a cable is similar to programming devices in system. figure 13?22 shows jtag configuration of a single cyclone ii device using a download cable. figure 13?22. jtag configurat ion of a single device using a download cable notes to figure 13?22 : (1) the pull-up resistor should be connected to the sa me supply voltage as the usb-blaster, masterblaster ( vio pin), byteblaster ii, or byteblastermv cable. (2) connect the nconfig and msel[1..0] pins to support a non-jtag conf iguration scheme. if only jtag configuration is used, connect the nconfig pin to v cc , and the msel[1..0] pins to ground. in addition, pull dclk and data0 to either high or low, whiche ver is convenient on your board. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable data sheet for this value. in the byteblastermv, this pin is a no connect. in the usb-blaster and byteblaster ii, this pin is connected to nce when it is used for as programming, otherwise it is a no connect. (4) nce must be connected to gnd or driven low for successful jtag configuration. (5) the nceo pin can be left unconnected or used as a user i/o pin when it does not feed other device?s nce pin. to configure a single device in a jt ag chain, the programming software places all other devices in bypass mode. in bypass mode, cyclone ii devices pass programming data from the tdi pin to the tdo pin through a single bypass register without being affected internally. this scheme nce nceo n.c. (5) msel0 msel1 nconfig conf_done v cc (1) gnd v cc gnd v cc (2) (2) (4) (1) (1) (1) (1) (2) 10 k 10 k nstatus usb-blaster, byteblaster ii, masterblaster, or byteblastermv 10-pin male header (top view) tck tdo tms tdi gnd vio (3) cyclone ii device data0 dclk (2) (2) pin 1 v cc 1 k v cc 1 k 1 k gnd
13?56 altera corporation cyclone ii device handbook, volume 1 february 2007 jtag configuration enables the programming software to program or verify the target device. configuration data driven into the target device appears on the tdo pin one clock cycle later. the quartus ii software verifies su ccessful jtag configuration upon completion. at the end of configur ation, the software checks the conf_done pin through the jtag port. when the quartus ii software generates a jam file for a multiple devi ce chain, it contains instructions so that all the devices in the chain are initialized at the same time. if conf_done is not high, the quartus i i software indicates that configuration has failed. if the conf_done pin transitions high, the software indicates that configur ation was successful. after the configuration bitstream is tran smitted serially via the jtag tdi port, the tck port is clocked an additional 299 cycles to perform cyclone ii device initialization. the enable user-supplied start-up clock (clkusr) option has no affect on the device initialization since this option is disabled in the sof when configuring the fpga in jtag us ing the quartus ii programmer and download cable. therefore, if you turn on the clkusr option, you do not need to provide a clock on clkusr when you are configuring the fpga with the quartus ii programm er and a download cable. cyclone ii devices have dedicated jtag pins that always function as jtag pins. you can perform jtag testing on cyclone ii devices before, after, and during configuration. cyclone ii devices support the bypass, idcode and sample instructions during configuration without interruption. all other jtag instruct ions may only be issued by first interrupting configuration and re programming i/o pins using the config_io instruction. the config_io instruction allows i/o buffers to be configured via the jtag port. the config_io instruction interrupts configuration. this instruction allows you to perform board-level testing before configuring the cyclone ii device or waiting for a configuration device to complete configuration. if you interrupt configuration, the cyclone ii device must be reconfigured via jtag ( pulse_config instruction) or by pulsing nconfig low after jtag testing is complete. f for more information, see the morphio: an i/o reconfiguration solution for altera white paper . the chip-wide reset ( dev_clrn ) and chip-wide output enable ( dev_oe ) pins on cyclone ii devices do not affect jtag boundary-scan or programming operations. toggling th ese pins does not affect jtag operations (other than the usual boundary-scan operation).
altera corporation 13?57 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices when designing a cyclone ii board for jtag configuration, use the guidelines in table 13?10 for the placement of the dedicated configuration pins. figure 13?23 shows jtag configuration of a cyclone ii device with a microprocessor. table 13?10. dedicated configurati on pin connections during jtag configuration signal description nce on all cyclone ii devices in the chain, nce should be driven low by connecting it to ground, pull ing it low via a resistor, or driving it by some control circuitr y. for devices that are also in multiple device as, or ps configuration chains, the nce pins should be connected to gnd duri ng jtag configuration or jtag configured in the same or der as the configuration chain. nceo on all cyclone ii devices in the chain, nceo can be used as a user i/o or connected to the nce of the next device. if nceo is connected to the nce of the next device, the nceo pin must be pulled high to v ccio by an external 10-k pull-up resistor to help the internal weak pull-up resistor. if the nceo pin is not connected to the nce pin of the next device, you can use it as a user i/o pin after configuration. msel these pins must not be left floating. these pins support whichever non-jtag c onfiguration is used in production. if only jtag configuration is used , you should tie these pins to ground. nconfig driven high by connecting to v cc , pulling up via a resistor, or driven high by some control circuitry. nstatus pull to v cc via a 10-k resistor. when configuring multiple devices in the same jtag chain, each nstatus pin should be pulled up to v cc individually. nstatus pulling low in the middle of jtag configuration indicates that an error has occurred. conf_done pull to v cc via a 10-k resistor. when configuring multiple devices in the same jtag chain, each conf_done pin should be pulled up to v cc individually. conf_done going high at the end of jtag config uration indicates successful configuration. dclk should not be left floating. drive lo w or high, whichever is more convenient on your board.
13?58 altera corporation cyclone ii device handbook, volume 1 february 2007 jtag configuration figure 13?23. jtag configurat ion of a single device using a microprocessor notes to figure 13?23 : (1) the pull-up resistor sho uld be connected to a supply that provides an acceptable input signal for all devices in the chain. (2) connect the nconfig and msel[1..0] pins to support a non-jtag configuration scheme. if only jtag configuration is used, connect the nconfig pin to v cc , and the msel[1..0] pins to ground. in addition, pull dclk and data0 to either high or low, whichever is convenient on your board. (3) nce must be connected to gnd or driven low for successful jtag configuration. (4) if using an epcs4 or epcs1 device, set msel[1..0] to 00 . see table 13?4 for more details. jtag configuration of multiple devices when programming a jtag device ch ain, one jtag-compatible header is connected to several devices. the number of devices in the jtag chain is limited only by the drive capabilit y of the download cable. when four or more devices are connected in a jtag chain, altera recommends buffering the tck, tdi, and tms pins with an on-board buffer. jtag-chain device programming is ideal when the system contains multiple devices, or when testing your system using jtag bst circuitry. figure 13?24 shows multiple device jtag configuration. nconfig data0 dclk tdi tck tms microprocessor memory addr data tdo cyclone ii fpga nstatus conf_done v cc v cc 10 k 10 k (2) (2) (4) (2) (2) (1) (1) (3) (2) msel1 msel0 nce nceo
altera corporation 13?59 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices figure 13?24. jtag configuration of mult iple devices using a download cable notes to figure 13?24 : (1) the pull-up resistor should be conne cted to the same supply voltage as the usb-blaster, masterblaster (vio pin), byteblaster ii or byteblastermv cable. (2) connect the nconfig and msel[1..0] pins to support a non-jtag conf iguration scheme. if only jtag configuration is used, connect the nconfig pin to v cc , and the msel[1..0] pins to ground. in addition, pull dclk and data0 to either high or low, whiche ver is convenient on your board. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable data sheet for this value. in the byteblastermv cable, this pin is a no connect. in the usb-blaster and byteblaster ii cable, this pin is connected to nce when it is used for as programming, otherwise it is a no connect. (4) nce must be connected to ground or driven low for successful jtag configuration. connect the nce pin to gnd or pull it low during jtag configuration. in multiple device as and ps configuratio n chains, connect the first device's nce pin to gnd and connect its nceo pin to the nce pin of the next device in the chain or you can use it as a user i/o pin after configuration. after the first device completes configuration in a multiple device configuration chain, its nceo pin drives low to activate the second device?s nce pin, which prompts the second device to begin configuration. therefore, if these devices are also in a jtag chain, you should make sure the nce pins are connected to gnd during jtag configuration or that the devices are jtag configured in the same order as the configuration chain. as long as the devices are jtag configured in the same order as the multiple device configuration chain, the nceo pin of the previous device drives the nce pin of the next device low when it has successfully been jtag configured. tms tck usb-blaster, byteblaster ii, masterblaster, or byteblastermv 10-pin male header tdi tdo vcc v cc v cc pin 1 nstatus nconfig msel1 nce v cc conf_done v cc tms tck tdi tdo nconfig msel1 nce v cc conf_done v cc tms tck tdi tdo nconfig msel1 nce v cc conf_done v cc (2) (2) msel0 (2) (2) (2) msel0 (2) (2) dclk dclk dclk (2) (2) (2) data0 data0 data0 (2) (2) (1) (1) (1) (1) (1) (1) (4) (4) (4) (2) (2) msel0 (2) nceo nceo nceo vio (3) cyclone ii fpga cyclone ii fpga cyclone ii fpga nstatus nstatus 10 k 1 k 1 k 1 k 10 k 10 k 10 k 10 k 10 k
13?60 altera corporation cyclone ii device handbook, volume 1 february 2007 jtag configuration 1 the quartus ii software sets the cyclone ii device nceo pin as an output pin driving to ground by default. if the nceo pin inputs to the next device?s nce pin, make sure that the nceo pin is not used as a user i /o pin after configuration. other altera devices that have jtag support can be placed in the same jtag chain for device prog ramming and configuration. f for more information on configuring multiple altera devices in the same configuration chain, see the configuring mixed altera fpga chains chapter in the configuration handbook . jam stapl jam stapl, jedec standard jesd-71, is a standard file format for in- system programmability (isp). jam stapl supports programming or configuration of programmable device s and testing of electronic systems using the ieee 1149.1 jtag interface. jam stapl is a freely licensed open standard. the jam player provides an interface for manipulating the ieee std. 1149.1 jtag tap state machine. f for more information on jtag and jam stapl in embedded environments, see an 122: using jam stapl for isp & icr via an embedded processor . to download the jam player, go to the altera web site ( www.altera.com ). configuring cyclone ii fpgas with jrunner jrunner is a software driver that allows you to configure cyclone ii devices through the byteblaster ii or byteblastermv cables in jtag mode. the programming inpu t file supported is in .rbf format. jrunner also requires a chai n description file ( .cdf ) generated by the quartus ii software. jrunner is targeted for embedded jtag configuration. the source code has been developed for the windows nt operating system (os). you can customize the code to make it run on your embedded platform. 1 the rbf file used by the jrunner software driver can not be a compressed rbf file because jrunner uses jtag-based configuration. during jtag-based configuration, the real-time decompression feature is not available. f for more information on the jrunner software driver, see jrunner software driver: an embedded solution for pld jtag configuration and the source files on the altera web site.
altera corporation 13?61 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices combining jtag & active seri al configuration schemes you can combine the as configuration scheme with jtag-based configuration. set the msel[1..0] pins to 00 (as mode) or 10 (fast as mode)in this setup, which uses two 10 -pin download cable headers on the board. the first header programs the serial configuration device in the system via the as programming in terface, and the second header configures the cyclone ii directly via the jtag interface. if you try configuring the device using both schemes simultaneously, jtag configuration takes preced ence and as configuration is terminated. when a blank serial configuration devi ce is attached to cyclone ii device, turn on the halt on-chip config uration controller option under the tools menu by clicking options . the options dialog box appears. in the category list, select programmer before starting the jtag configuration with the quartus ii programmer . this option stops the as reconfiguration loop from a blank se rial configuration device before starting the jtag configuration. th is includes using the serial flash loader ip because jtag is used for configuring the cyclone ii device. users do not need to recompile their quartus ii designs after turning on this option. programming serial configuratio n devices in-sys tem using the jtag interface cyclone ii devices in a single device chain or in a multiple device chain support in-system progra mming of a serial configuration device using the jtag interface via the serial flash loader design. the board?s intelligent host or download cable can use the four jtag pins on the cyclone ii device to program the serial configuration device in system, even if the host or download ca ble cannot access the configuration device?s configuration pins ( dclk , data , asdi , and ncs pins). the serial flash loader design is a jtag-based in-system programming solution for altera serial configuratio n devices. the serial flash loader is a bridge design for the fpga that uses its jtag interface to access the epcs jic (jtag indirect configuration device programming) file and then uses the as interface to prog ram the epcs device. both the jtag interface and as interface are bridge d together inside the serial flash loader design. in a multiple device chain, you only need to configure the master cyclone ii device which is controlling the serial configuration device. the slave devices in the multiple device chain which are configured by the serial configuration device do not need to be configured when using this
13?62 altera corporation cyclone ii device handbook, volume 1 february 2007 jtag configuration feature. to use this feature successfully, set the msel[1..0] pins of the master cyclone ii device to select the as configuration scheme or fast as configuration scheme (see table 13?1 ). 1 the quartus ii software version 4.1 and higher supports serial configuration device isp through an fpga jtag interface using a jic file. the serial configuration device in-system programming through the cyclone ii jtag interface has three stages, which are described in the following sections. loading the serial flash loader design the serial flash loader design is a de sign inside the cyclone ii device that bridges the jtag interface and as interface inside the cyclone ii device using glue logic. the intelligent host uses the jtag interface to configure the master cyclone ii device with a serial flash lo ader design. the se rial flash loader design allows the master cyclone ii de vice to control the access of four serial configuration device pins, also known as the active serial memory interface (asmi) pins, through the jtag interface. the asmi pins are the serial clock input ( dclk ), serial data output ( data ), as data input ( asdi ), and an active-low chip select ( ncs ) pins. if you configure a master cyclone ii device with a serial flash loader design, the master cyclone ii device ca n enter user mode even though the slave devices in the multiple device chain are not being configured. the master cyclone ii device can enter user mode with a serial flash loader design even though the conf_done signal is externally held low by the other slave devices in chain. figure 13?25 shows the jtag configuration of a single cyclone ii device with a serial flash loader design.
altera corporation 13?63 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices figure 13?25. jtag configurat ion of a single device using a download cable notes to figure 13?25 : (1) the pull-up resistor should be connected to the same supply voltage as the usb blaster, masterblaster (v io pin), byteblaster ii, or byteblastermv cable. (2) the nconfig , msel[1..0] pins should be connected to support a non- jtag configuration scheme. if only jtag configuration is used, connect nconfig to v cc , and msel[1..0] to ground. pull dclk either high or low, whichever is convenient on your board. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . refer to the masterblaster serial/usb communications cable data sheet for this value. in the byteblastermv cable, this pin is a no connect. in the usb blaster and byteblaster ii cables, this pin is connected to nce when it is used for active serial programmin g, otherwise it is a no connect. (4) nce must be connected to gnd or driven low for successful jtag configuration. isp of serial configuration device in the second stage, the serial flash loader design in the master cyclone ii device allows you to write the configuration data for the device chain into the serial configuration device by using the cyclone ii jtag interface. the jtag interface sends the programming data for the serial configuration device to the cyclone ii device first. the cyclone ii device then uses the asmi pins to transmit the data to the serial configuration device. nce (4) msel0 nconfig conf_done v cc (1) v cc gnd v cc (1) gnd v cc (1) (2) v cc (1) 1 k 10 k v cc (1) 10 k 10 k 1 k nstatus pin 1 usb blaster, byteblaster ii, masterblaster, or byteblastermv 10-pin male header (top view) gnd tck tdo tms tdi 1 k gnd v io (3) cyclone ii device nce0 n.c. msel1 dclk ncso asdo data 0 dclk ncs asdi data (2) serial configuration device serial flash loader
13?64 altera corporation cyclone ii device handbook, volume 1 february 2007 device configuration pins reconfiguration after all the configuration data is written into the serial configuration device successfully, the cyclone ii device does not reconfigure by itself. the intelligent host issues the pulse_nconfig jtag instruction to initialize the reconfiguration process. during reconfiguration, the master cyclone ii device is reset and the serial flash loader design no longer exists in the cyclone ii device and the serial configuration device configures all the devices in th e chain with your user design. device configuration pins this section describes the connecti ons and functionality of all the configuration related pins on the cyclone ii device. table 13?11 describes the dedicated configuration pins, which are required to be connected properly on your board for successful configuration. some of these pins may not be required for your configuration schemes. table 13?11. dedicated configuration pins on the cyclone ii device (part 1 of 5) pin name user mode configuration scheme pin type description msel[1..0] n/a all input this pin is a two-bit configuration input that sets the cyclone ii device configuration scheme. see table 13?1 for the appropriate settings. you must connect these pins to v ccio or ground. the msel[1..0] pins have 9-k internal pull-down resistors that are always active. nconfig n/a all input this pin is a configurat ion control input. if this pin is pulled low during user mode, the fpga loses its configuration data, enters a reset state, and tri-states all i/o pins. transitioning this pin high initiates a reconfiguration. if your configuration scheme uses an enhanced configuration device or epc2 device, you can connect the nconfig pin directly to v cc or to the configuration device's ninit_conf pin. the input buffer on this pi n supports hysteresis using schmitt trigger circuitry.
altera corporation 13?65 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices nstatus n/a all bidirectional open-drain the cyclone ii device drives nstatus low immediately after power-up and releases it after the por time. this pin provides a status output and input for the cyclone ii device. if the cyclone ii device detects an error during configuration, it drives the nstatus pin low to stop configuration. if an external source (for example, another cyclone ii device) drives the nstatus pin low during configuration or initialization, the target device enters an error state. driving nstatus low after configuration and initialization does not affect the configured device. if your design uses a configuration device, driving nstatus low causes the configuration device to attempt to configure the fpga, but since the fpga ignores transitions on nstatus in user mode, the fpga does not reconfigure. to initiate a reconfiguration, pull the nconfig pin low. the enhanced configuration devices? and epc2 devices? oe and ncs pins are connected to the cyclone ii device?s nstatus and conf_done pins, respectively, and have optional internal programmable pull-up resistors. if you use these internal pull-up resi stors on the enhanced configuration device, do not use external 10-k pull- up resistors on these pins. when using epc2 devices, you should only use external 10-k pull-up resistors. the input buffer on this pi n supports hysteresis using schmitt trigger circuitry. table 13?11. dedicated configuration pins on the cyclone ii device (part 2 of 5) pin name user mode configuration scheme pin type description
13?66 altera corporation cyclone ii device handbook, volume 1 february 2007 device configuration pins conf_done n/a all bidirectional open-drain this pin is a status output and input. the target cyclone ii device drives the conf_done pin low before and during configuration. once the cyclone ii device receives all the configuration data without error and the initialization cycle starts, it releases conf_done . driving conf_done low during user mode does not affect the configured device. do not drive conf_done low before the device enters user mode. after the cyclone ii device receives all the data, the conf_done pin transitions high, and the device initializes and enters user mode. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. driving conf_done low after configuration and initialization does not affect the configured device. the enhanced configuration devices? and epc2 devices? oe and ncs pins are connected to the cyclone ii device?s nstatus and conf_done pins, respectively, and have optional internal programmable pull-up resistors. if internal pull-up resistors on the enhanced configuration device are used, external 10-k pull-up resistors should not be used on these pins. when using epc2 devices, you should only use external 10-k pull-up resistors. the input buffer on this pi n supports hysteresis using schmitt trigger circuitry. nce n/a all input this pin is an active-low chip enable. the nce pin activates the device with a low signal to allow configuration. the nce pin must be held low during configuration, initialization, and user mode. in single device configuration, it s hould be tied low. in multiple device configuration, nce of the first device is tied low while its nceo pin is connected to nce of the next device in the chain. the nce pin must also be held low for successful jtag programming of the fpga. the input buffer on this pi n supports hysteresis using schmitt trigger circuitry. table 13?11. dedicated configuration pins on the cyclone ii device (part 3 of 5) pin name user mode configuration scheme pin type description
altera corporation 13?67 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices nceo n/a if option is on. i/o if option is off. all output this pin is an output that drives low when device configuration is complete. in single device configuration, you can leave this pin floating or use it as a user i/o pin after configuration. in multiple device configuration, this pin inputs the next device's nce pin. the nceo of the last device in the chain can be left floating or used as a user i/o pin after configuration. if you use the nceo pin to feed next device?s nce pin, use an external 10-k pull-up resistor to pull the nceo pin high to the v ccio voltage of its i/o bank to help the internal weak pull-up resistor. use the quartus ii software to make this pin a user i/o pin. asdo n/a in as mode i/o in ps and jtag mode as output this pin sends a cont rol signal from the cyclone ii device to the serial configuration device in as mode and is used to read out configuration data. in as mode, asdo has an internal pull-up that is always active. ncso n/a in as mode i/o in ps and jtag mode as output this pin sends an output control signal from the cyclone ii device to the serial configuration device in as mode that enables the configuration device. in as mode, ncso has an internal pull-up resistor that is always active. table 13?11. dedicated configuration pins on the cyclone ii device (part 4 of 5) pin name user mode configuration scheme pin type description
13?68 altera corporation cyclone ii device handbook, volume 1 february 2007 device configuration pins dclk n/a ps, as input (ps) output (as) in ps configuration, dclk is the clock input used to clock data from an external source into the target device. data is latched into the cyclone ii device on the rising edge of dclk . in as mode, dclk is an output from the cyclone ii device that provides timing for the configuration interface. in as mode, dclk has an internal pull-up that is always active. after configuration, this pi n is tri-stated. if you are using a configuration device, it drives dclk low after configuration is complete. if your design uses a control host, drive dclk either high or low. toggling this pin after configuration does not affect the configured device. the input buffer on this pi n supports hysteresis using schmitt trigger circuitry. data0 n/a all input this is the data input pin. in serial configuration modes, bit-wide configurati on data is presented to the target device on the data0 pin. in as mode, data0 has an internal pull-up resistor that is always active. after configuration, epc1 and epc1441 devices tri-state this pin, while enhanced configuration and epc2 devices drive this pin high. the input buffer on this pi n supports hysteresis using schmitt trigger circuitry. table 13?11. dedicated configuration pins on the cyclone ii device (part 5 of 5) pin name user mode configuration scheme pin type description
altera corporation 13?69 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices table 13?12 describes the optional configur ation pins. if these optional configuration pins are not enabled in the quartus ii software, they are available as general-purpose us er i/o pins. therefore during configuration, these pins function as user i/o pins and are tri-stated with weak pull-up resistors. table 13?12. optional configuration pins pin name user mode pin type description clkusr n/a if option is on. i/o if option is off. input this is an optional user -supplied clock input that synchronizes the initialization of one or more devices. this pin is enabled by turning on the enable user-supplied start-up clock (clkusr) option in the quartus ii software init_done n/a if option is on. i/o if option is off. output open- drain this is a status pin that can be used to indicate when the device has initialized and is in user mode. when nconfig is low and during the beginning of configuration, the init_done pin is tri-stated and pulled high due to an external 10-k pull-up resistor. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin goes low. when initialization is complete, the init_done pin is released and pulled hi gh and the fpga enters user mode. thus, the monitoring circuitry must be able to detect a low-to-high transition. this pin is enabled by turning on the enable init_done output option in the quartus ii software. dev_oe n/a if option is on. i/o if option is off. input optional pin that allows the us er to override all tri-states on the device. when this pin is dr iven low, all i/o pins are tri- stated. when this pin is driv en high, all i/o pins behave as programmed. this pin is enabled by turning on the enable device-wide output enable (dev_oe) option in the quartus ii software. dev_clrn n/a if option is on. i/o if option is off. input optional pin that allows you to override al l clears on all device registers. when this pi n is driven low, all registers are cleared. when this pin is driven high, all registers behave as programmed. this pin is enabled by turning on the enable device-wide reset (dev_clrn) option in the quartus ii software.
13?70 altera corporation cyclone ii device handbook, volume 1 february 2007 conclusion table 13?13 describes the dedicated jtag pins. jtag pins must be kept stable before and during configuratio n to prevent accidental loading of jtag instructions. the tck pin has a weak internal pull-down resistor and the tdi and tms jtag input pins have weak internal pull-up resistors. conclusion cyclone ii devices can be configured in as, ps or jtag configuration schemes to fit your system's need. the as configuration scheme supported by cyclone ii devices can now operate at a higher dclk table 13?13. dedicated jtag pins pin name user mode pin type description tdi n/a input serial input pin for instructi ons as well as test and programming data. data is shifted in on the rising edge of tck. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to v cc . the input buffer on this pin s upports hysteresis using schmitt trigger circuitry. tdo n/a output serial data output pin for instructions as well as test and programming data. data is shifted out on the falling edge of tck. the pin is tri-stated if data is not being shifted out of the device. if the jtag interface is not required on the board, the jtag circuitry can be disabled by leaving this pin unconnected. tms n/a input input pin that provides the control signal to determine the transitions of the tap controller state machine. transitions within the state machine occur on the rising edge of tck. therefore, tms must be set up before the rising edge of tck. tms is evaluated on the rising edge of tck. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to v cc . the input buffer on this pin s upports hysteresis using schmitt trigger circuitry. tck n/a input the clock input to the bst circuitry. some operations occur at the rising edge, while others occur at the falling edge. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to gnd. the input buffer on this pin s upports hysteresis using schmitt trigger circuitry.
altera corporation 13?71 february 2007 cyclone ii device handbook, volume 1 configuring cyclone ii devices frequency (up to 40 mhz), which reduces your configuration time. in addition, cyclone ii devices can receive a compressed configuration bitstream and decompress this da ta on-the-fly in the as or ps configuration scheme, which further reduces storage requirements and configuration time.
13?72 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history document revision history table 13?14 shows the revision history for this document. table 13?14. document revision history date & document version changes made summary of changes february 2007 v3.1 added document revision history. added note (1) to table 13?1 . added note (1) to table 13?4 . updated figure 13?3 . updated figures 13?6 and 13?7 . updated note (2) to figure 13?13 . updated ?single device ps configuration using a configuration device? section. updated note (2) to figure 13?14 . updated note (2) to figure 13?15 . updated note (2) to figure 13?16 . updated note (2) to figure 13?17 . updated note (4) to figure 13?21 . updated note (2) to figure 13?25 . changed unit ?kw? to ?k ? in figures 13?6 and 13?7 . added note about serial configuration devices supporting 20 mhz and 40 mhz dclk . added infomation about the need for a resistor on nconfig if reconfiguration is required. added information about msel[1..0] internal pull-down resistor value. july 2005 v2.0 updated ?configuration stage? section. updated ?ps configuration using a download cable? section. updated figures 13?8 , 13?12 , and 13?18 . november 2004 v1.1 updated ?configuration stage? section in ?single device as configuration? section. updated ?initialization stage? section in ?single device as configuration? section. updated figure 13?8 . updated ?initialization stage? section in ?single device ps configuration using a max ii device as an external host? section. updated table 13?7 . updated ?single device ps configuration using a configuration device? section. updated ?initialization stage? section in ?single device ps configuration using a configuration device? section. updated figure 13?18 . updated ?single device jtag configuration? section. june 2004 v1.0 added document to the cyclone ii device handbook.
altera corporation 14?1 february 2007 14. ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices introduction as printed circuit boards (pcbs) become more complex, the need for thorough testing becomes increasingly important. advances in surface- mount packaging and pcb manufacturing have resulted in smaller boards, making traditional test methods (e.g., external test probes and ?bed-of-nails? test fixtures) harder to implement. as a result, cost savings from pcb space reductions are sometimes offset by cost increases in traditional testing methods. in the 1980s, the joint test action gr oup (jtag) developed a specification for boundary-scan testing that was later standardized as the ieee std. 1149.1 specification. this bo undary-scan test (b st) architecture offers the capability to efficiently test components on pcbs with tight lead spacing. this bst architecture tests pin connections without using physical test probes and captures functional data while a device is operating normally. boundary-scan cells in a device force signals onto pins or capture data from pin or logic array signals. forced test data is serially shifted into the boundary-scan cells. captured data is serially shifted out and externally compared with expected results. figure 14?1 shows the concept of boundary-scan testing. figure 14?1. ieee std. 1149.1 boundary-scan testing core logic serial data in boundary-scan cell ic core logic serial data out jtag device 1 jtag device 2 pin signal tested connection cii51014-2.1
14?2 altera corporation cyclone ii device handbook, volume 1 february 2007 ieee std. 1149.1 bst architecture this chapter discusses how to use th e ieee std. 1149.1 bst circuitry in cyclone ? ii devices, including: ieee std. 1149.1 bst architecture ieee std. 1149.1 boun dary-scan register ieee std. 1149.1 bst operation control i/o voltage support in jtag chain using ieee std. 1149.1 bst circuitry disabling ieee std. 1149.1 bst circuitry guidelines for ieee std. 1149.1 boundary-scan testing boundary-scan description language (bsdl) support in addition to bst, you can use the ieee std. 1149.1 controller for cyclone ii device in-circuit reconfiguration (icr). however, this chapter only discusses the bst feature of the ieee std. 1149.1 circuitry. f for information on configuring cyclone ii devices via the ieee std. 1149.1 circuitry, see the configuring cyclone ii devices chapter in volume 1 of the cyclone ii device handbook . ieee std. 1149.1 bst architecture a cyclone ii device operating in ie ee std. 1149.1 bst mode uses four required pins, tdi , tdo , tms and tck . the optional trst pin is not available in cyclone ii devices. tdi and tms pins have weak internal pull-up resistors while tck has weak internal pull-down resistors. all user i/o pins are tri-stated during jtag configuration. table 14?1 summarizes the functions of each of these pins. table 14?1. ieee std. 1149.1 pin descriptions pin description function tdi test data input serial input pin for instruct ions as well as test and programming data. signal applied to tdi is expected to change state at the falling edge of tck . data is shifted in on the rising edge of tck . tdo test data output serial data output pin for inst ructions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. tms test mode select input pin that provides the control signal to determine the transitions of the tap controller state machine. trans itions within the state machine occur at the rising edge of tck . therefore, tms must be set up before the rising edge of tck . tms is evaluated on the rising edge of tck . during non-jtag operation, tms is recommended to be driven high. tck test clock input the clock input to the bst circuitry. some operations occur at the rising edge, while others occur at the falling edge. the clock input waveform should have a 50% duty cycle.
altera corporation 14?3 february 2007 cyclone ii device handbook, volume 1 ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices the ieee std. 1149.1 bst circuitry requires the following registers: the instruction register determines the action to be performed and the data register to be accessed. the bypass register is a 1-bit-long data register that provides a minimum-length serial path between tdi and tdo . the boundary-scan register is a sh ift register composed of all the boundary-scan cells of the device. figure 14?2 shows a functional model of the ieee std. 1149.1 circuitry. figure 14?2. ieee std. 1149.1 circuitry note to figure 14?2 : (1) for register lengths, see the device data sheet in the configuration & testing chapter in volume 1 of the cyclone ii device handbook. ieee std. 1149.1 boundary-scan testing is controlled by a test access port (tap) controller. for more information on the tap controller, see ?ieee std. 1149.1 bst operation control? on page 14?6 . the tms and tck pins updateir clockir shiftir updatedr clockdr shiftdr tdi instruction register bypass register boundary-scan register instruction decode tms tclk ta p controller icr registers tdo data registers device id register (1) (1)
14?4 altera corporation cyclone ii device handbook, volume 1 february 2007 ieee std. 1149.1 boundary-scan register operate the tap controller, and the tdi and tdo pins provide the serial path for the data registers. the tdi pin also provides data to the instruction register, which then ge nerates control logic for the data registers. ieee std. 1149.1 boundary-scan register the boundary-scan register is a large serial shift register that uses the tdi pin as an input and the tdo pin as an output. the boundary-scan register consists of 3-bit peripheral elements that are associated with cyclone ii i/o pins. you can use the boundary-sca n register to test external pin connections or to capture internal data. f see the configuration & testing chapter in volume 1 of the cyclone ii device handbook for the cyclone ii device boundary-scan register lengths. figure 14?3 shows how test data is serially shifted around the periphery of the ieee std. 1149.1 device. figure 14?3. boundary-scan register boundary-scan cells of a cyclone ii device i/o pin the cyclone ii device 3-bit boundary-sca n cell (bsc) consists of a set of capture registers and a set of update registers. the capture registers can connect to internal device data via the outj and oej signals, and connect tck tms tap controller tdi internal logic tdo each peripheral element is either a n i/o pin, dedicated input pin, or dedicated configuration pin.
altera corporation 14?5 february 2007 cyclone ii device handbook, volume 1 ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices to external device data via the pin_in signal, while the update registers connect to external data through the pin_out and pin_oe signals. the global control signals for the ieee std. 1149.1 bst registers (for example, shift, clock, and update) are generate d internally by the tap controller. the mode signal is generated by a decode of the instruction register. the data signal path for the boundary-scan register runs from the serial data in ( sdi ) signal to the se rial data out ( sdo ) signal. the scan register begins at the tdi pin and ends at the tdo pin of the device. figure 14?4 shows the cyclone ii device?s user i/o boundary-scan cell. figure 14?4. cyclone ii device's user i/o bs c with ieee std. 1149.1 bst circuitry 0 1 dq output dq oe dq input dq input dq output dq oe from or to device i/o cell circuitry and/or logic array 0 1 0 1 0 1 0 1 0 1 0 1 pin_out inj oej outj v cc sdo pin shift sdi clock update highz mode pin_oe pin_in output buffer capture registers update registers global signals
14?6 altera corporation cyclone ii device handbook, volume 1 february 2007 ieee std. 1149.1 bst operation control table 14?2 describes the capture and update register capabilities of all types of boundary-scan cell s within cyclone ii devices. ieee std. 1149.1 bst operation control cyclone ii devices implement the following ieee std. 1149.1 bst instructions: sample/preload , extest , bypass , idcode , usercode , clamp, and highz . the bst instruction length is 10 bits. these instructions are described later in this chapter. f for summaries of the bst instructions and their instruction codes, see the configuration & testing chapter in volume 1 of the cyclone ii device handbook . the ieee std. 1149.1 test access po rt (tap) controller, a 16-state state machine clocked on the rising edge of tck , uses the tms pin to control ieee std. 1149.1 oper ation in the device. figure 14?5 shows the tap controller state machine. table 14?2. cyclone ii device bound ary scan cell descriptions note (1) pin type captures drives comments output capture register oe capture register input capture register output update register oe update register input update register user i/o pins outj oej pin_in pin_out pin_oe inj dedicated clock input 01 pin_in n.c. (2) n.c. (2) n.c. (2) pin_in drives to clock network or logic array dedicated input (3) 01 pin_in n.c. (2) n.c. (2) n.c. (2) pin_in drives to control logic dedicated bidirectional (open drain) (4) 0 oej pin_in n.c. (2) n.c. (2) n.c. (2) pin_in drives to configuration control dedicated bidirectional (5) outj oej pin_in n.c. (2) n.c. (2) n.c. (2) outj drives to output buffer notes to table 14?2 : (1) tdi , tdo , tms , tck , all v cc and gnd pin types do not have bscs. (2) n.c.: no connect. (3) this includes nconfig , msel0 , msel1 , data0 , and nce pins and dclk (when not used in active serial mode). (4) this includes conf_done and nstatus pins. (5) this includes dclk (when not used in active serial mode).
altera corporation 14?7 february 2007 cyclone ii device handbook, volume 1 ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices figure 14?5. ieee std. 1149.1 tap controller state machine select_dr_scan capture_dr shift_dr exit1_dr pause_dr exit2_dr update_dr shift_ir exit1_ir pause_ir exit2_ir update_ir tms = 0 tms = 0 tms = 0 tms = 1 tms = 0 tms = 1 tms = 1 tms = 0 tms = 1 tms = 0 tms = 1 tms = 1 tms = 0 tms = 0 tms = 1 tms = 1 tms = 0 tms = 1 tms = 0 tms = 0 tms = 1 tms = 0 tms = 0 tms = 1 tms = 0 run_test/ idle tms = 0 test_logic/ reset tms = 1 tms = 0 tms = 1 tms = 1 tms = 1 tms = 1 capture_ir select_ir_sca n
14?8 altera corporation cyclone ii device handbook, volume 1 february 2007 ieee std. 1149.1 bst operation control when the tap controller is in the test_logic/reset state, the bst circuitry is disabled, the device is in normal operation, and the instruction register is initialized with idcode as the initial instruction. at device power-up, the tap controller starts in this test_logic/reset state. in addition, forcing the tap controller to the test_logic/reset state is done by holding tms high for five tck clock cycles. once in the test_logic/reset state, the tap controller remains in this state as long as tms is held high (while tck is clocked). figure 14?6 shows the timing requirements for th e ieee std. 1149.1 signals. figure 14?6. ieee std. 1149.1 timing waveforms to start ieee std. 1149.1 operation, select an instruction mode by advancing the tap controller to the shift instruction register ( shift_ir ) state and shift in the appropriate instruction code on the tdi pin. the waveform diagram in figure 14?7 represents the entry of the instruction code into the instruction regi ster. it shows the values of tck , tms , tdi , tdo , and the states of the tap controller. from the reset state, tms is clocked with the pattern 01100 to advance the tap controller to shift_ir . tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz
altera corporation 14?9 february 2007 cyclone ii device handbook, volume 1 ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices figure 14?7. selecting the instruction mode the tdo pin is tri-stated in all states except in the shift_ir and shift_dr states. the tdo pin is activated at the first falling edge of tck after entering either of the shift states and is tri-stated at the first falling edge of tck after leaving either of the shift states. when the shift_ir state is activated, tdo is no longer tri-stated, and the initial state of the instruction register is shifted out on the falling edge of tck . tdo continues to shift out the contents of the instruction register as long as the shift_ir state is active. the tap controller remains in the shift_ir state as long as tms remains low. during the shift_ir state, an instruction code is entered by shifting data on the tdi pin on the rising edge of tck . the last bit of the instruction code must be clocked at th e same time that the next state, exit1_ir , is activated. set tms high to activate the exit1_ir state. once in the exit1_ir state, tdo becomes tri-stated again. tdo is always tri-stated except in the shift_ir and shift_dr states. after an instruction code is entered correctly, the tap controller advances to serially shift test data in one of seven modes ( sample/preload, extest, bypass, idcode, usercode, clamp, or highz ) that are described below. sample/preload instruction mode the sample/preload instruction mode allows you to take a snapshot of device data without interrupting norm al device operation. you can also use this instruction to preload the test data into the update registers prior to loading the extest instruction. figure 14?8 shows the capture, shift, and update phases of the sample/preload mode. tck tms tdi tdo tap_state shift_ir run_test/idle select_ir_scan select_dr_scan test_logic/reset capture_ir exit1_ir
14?10 altera corporation cyclone ii device handbook, volume 1 february 2007 ieee std. 1149.1 bst operation control figure 14?8. ieee std. 1149.1 bst sample/preload mode 1 0 dq dq 1 0 1 0 1 0 dq dq 1 0 dq dq 1 0 outj oej mode inj capture registers update registers sdo sdi shift clock update 1 0 dq dq 1 0 1 0 1 0 dq dq 1 0 dq dq 1 0 outj oej sdi shift clock update mode sdo inj capture registers update registers capture phase in the capture phase, the signals at the pin, oej and outj, are load ed into the capture registers. the clock signals are supplied by the tap controllers clockdr output. the data retained in these registers consists of signals from normal device operation. shift & update phases in the shift phase, the previously captured signals at the pin, oej and outj, are shifted out of the boundary- scan register via the tdo pin using clock. as data is shifted out, the patterns for the next test can be shifted in via the tdi pin. in the update phase, data is transferred from the capture to the update registers using the update clock. the data stored in the update registers can be used for the extest instruction.
altera corporation 14?11 february 2007 cyclone ii device handbook, volume 1 ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices during the capture phase, multiplex ers preceding the capture registers select the active device data signals. this data is then clocked into the capture registers. the multiplexers at the outputs of the update registers also select active device data to pr event functional interruptions to the device. during the shift phase, the bo undary-scan shift register is formed by clocking data through capture registers around the device periphery, then out of the tdo pin. the device can simulta neously shift new test data into tdi and replace the contents of th e capture registers. during the update phase, data in the capture re gisters is transferred to the update registers. this data can then be used in the extest instruction mode. see ?extest instruction mode? on page 14?11 for more information. figure 14?9 shows the sample/preload waveforms. the sample/preload instruction code is shifted in through the tdi pin. the tap controller advances to the capture_dr state, then to the shift_dr state, where it remains if tms is held low. the data that was present in the capture registers after the capture phase is shifted out of the tdo pin. new test data shifted into the tdi pin appears at the tdo pin after being clocked through the entire boundary-scan register. figure 14?9 shows that the instruction code at tdi does not appear at the tdo pin until after the capture register data is shifted out. if tms is held high on two consecutive tck clock cycles, the tap co ntroller advances to the update_dr state for the update phase. figure 14?9. sample/preload shi ft data register waveforms extest instruction mode the extest instruction mode is used to check external pin connections between devices. unlike the sample/preload mode, extest allows test data to be forced onto the pin signals. by forcin g known logic high and low levels on output pins, opens and shorts can be detected at pins of any device in the scan chain. data stored in boundary-scan register is shifted out of tdo. after boundary-scan register data has been shifted out, data entered into tdi will shift out of tdo. update_ir shift_dr exit1_dr select_dr capture_dr exit1_ir update_dr shift_ir instruction code tck tms tdi tdo tap_state
14?12 altera corporation cyclone ii device handbook, volume 1 february 2007 ieee std. 1149.1 bst operation control figure 14?10 shows the capture, shift, and update phases of the extest mode. figure 14?10. ieee std. 1149.1 bst extest mode 1 0 dq dq 1 0 1 0 1 0 dq dq 1 0 dq dq 1 0 outj oej mode inj capture registers update registers sdi shift clock update sdo 1 0 dq dq 1 0 1 0 1 0 dq dq 1 0 dq dq 1 0 outj oej mode inj capture registers update registers sdi shift clock update sdo capture phase in the capture phase, the signals at the pin, oej and outj, are loaded into the capture registers. the clock signals are supplied by the tap controllers clockdr output. previously retained data in the update registers drive the pin_in, inj, and allows the i/o pin to tri-state or drive a signal out. a 1?in the oej update register tri-states the output buffer. shift & update phases in the shift phase, the previously captured signals at the pin, oej and outj, are shifted out of the boundary- scan register via the tdo pin using clock. as data is shifted out, the patterns for the next test can be shifted in via the tdi pin. in the update phase, data is transferred from the capture registers to the update registers using the update clock. the update registers then drive the pin_in, inj, and allow the i/o pin to tri- state or drive a signal out.
altera corporation 14?13 february 2007 cyclone ii device handbook, volume 1 ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices extest selects data differently than sample/preload . extest chooses data from the update registers as the source of the output and output enable signals. once the extest instruction code is entered, the multiplexers select the update register data. thus, data stored in these registers from a previous extest or sample/preload test cycle can be forced onto the pin signals. in the capt ure phase, the results of this test data are stored in the capture registers, then shifted out of tdo during the shift phase. new test data can then be stored in the update registers during the update phase. the extest waveform diagram in figure 14?11 resembles the sample/preload waveform diagram, except for the instruction code. the data shifted out of tdo consists of the data that was present in the capture registers after the capture phase. new test data shifted into the tdi pin appears at the tdo pin after being clocked through the entire boundary-scan register. figure 14?11. extest shift data register waveforms bypass instruction mode the bypass mode is activated when an instruction code of all 1?s is loaded in the instruction register. the waveforms in figure 14?12 show how scan data passes through a device once the tap controller is in the shift_dr state. in this state, data si gnals are clocked into the bypass register from tdi on the rising edge of tck and out of tdo on the falling edge of the same clock pulse. data stored in boundary-scan register is shifted out of tdo. after boundary-scan register data has been shifted out, data entered into tdi will shift out of tdo. update_ir shift_dr exit1_dr select_dr capture_dr exit1_ir update_dr shift_ir instruction code tck tms tdi tdo tap_state
14?14 altera corporation cyclone ii device handbook, volume 1 february 2007 ieee std. 1149.1 bst operation control figure 14?12. bypass shift data register waveforms idcode instruction mode the idcode instruction mode is used to identify the devices in an ieee std. 1149.1 chain. when idcode is selected, the device identification register is loaded with the 32-bit vendor-defined identification code. the device id register is connected between the tdi and tdo ports, and the device idcode is shifted out. the idcode for cyclone ii devices are listed in the configuration & testing chapter in volume 1 of the cyclone ii device handbook . usercode instruction mode the usercode instruction mode is used to examine the user electronic signature (ues) within the devices alon g an ieee std. 1149.1 chain. when this instruction is selected, the device identification register is connected between the tdi and tdo ports. the user-defined ues is shifted into the device id register in parallel from the 32-bit usercode register. the ues is then shifted out through the device id register. the ues value is not user defined until after the device has been configured. before configuration, the ues value is set to the default value. clamp instruction mode the clamp instruction mode is used to allow the boundary-scan register to determine the state of the si gnals driven from the pins. in clamp instruction mode, the bypass register is selected as the serial path between the tdi and tdo ports. data shifted into tdi on the rising edge of tck is shifted out of tdo on the falling edge of the same tck pulse. update_ir select_dr_scan capture_dr exit1_ir exit1_dr update_dr shift_dr instruction code tck tms tdi tdo tap_state shift_ir bit 2 bit 3 bit 1 bit 2 bit 4 bit 1
altera corporation 14?15 february 2007 cyclone ii device handbook, volume 1 ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices if you are testing the device after configuring it, the programmable weak pull-up resister or the bus hold feature overrides the clamp value (the value stored in the update register of the boundary-scan cell) at the pin. highz instruction mode the highz instruction mode is used to se t all of the user i/o pins to an inactive drive state. these pins are tri-stated until a new jtag instruction is executed. when this instruction is loaded into the instruction register, the bypass register is connected between the tdi and tdo ports. if you are testing the device after configuring it, the programmable weak pull-up resistor or the bus hold feature overrides the highz value at the pin. i/o voltage support in jtag chain a jtag chain can contain several diffe rent devices. however, you should be cautious if the chain contains devices that have different v ccio levels. the output voltage level of the tdo pin must meet the specifications of the tdi pin it drives. for cyclone ii devices, the tdo pin is powered by the v ccio power supply. since the v ccio supply is 3.3 v, the tdo pin drives out 3.3 v. devices can interface with each other although they might have different v ccio levels. for example, a device with a 3.3-v tdo pin can drive to a device with a 5.0-v tdi pin because 3.3 v meets the minimum ttl-level v ih for the 5.0-v tdi pin. jtag pins on cycl one ii devices can support 2.5- or 3.3-v input levels. f for more information on multivolt i/o support, see the cyclone ii architecture chapter in volume 1 of the cyclone ii device handbook . you can also interface the tdi and tdo lines of the devices that have different v ccio levels by inserting a level shifter between the devices. if possible, the jtag chain should be built such that a device with a higher v ccio level drives to a device with an equal or lower v ccio level. this way, a level shifter may be required only to shift the tdo level to a level acceptable to the jtag tester. figure 14?13 shows the jtag chain of mixed voltages and how a level shifter is inserted in the chain.
14?16 altera corporation cyclone ii device handbook, volume 1 february 2007 using ieee std. 1149.1 bst circuitry figure 14?13. jtag chai n of mixed voltages using ieee std. 1149.1 bst circuitry cyclone ii devices have dedicated jtag pins, and the ieee std. 1149.1 bst circuitry is enabled upon device power-up. you can perform bst on cyclone ii fpgas not only before and af ter configuration, but also during configuration. cyclone ii fpgas support the bypass , idcode, and sample instructions during configuration without interrupting configuration. to send all other jtag instructions, you must interrupt configuration using the config_io instruction. the config_io instruction allows you to configure i/o buffers via the jtag port, and when issued, interrupts configuration. this instruction allows you to perform board-level testing prior to configuring the cyclone ii fpga or waiting for a configuration device to complete configuration. once configuration has been interrupted and jtag bst is complete, the part must be reconfigured via jtag ( pulse_config instruction) or by pulsing nconfig low. when you perform jtag boundary-scan testing before configuration, the nconfig pin must be held low. the device-wide reset ( dev_clrn ) and device-wide output enable ( dev_oe ) pins on cyclone ii devices do not affect jtag boundary-scan or configuration operations . toggling these pins does not disrupt bst operation any more than usual. tester 3.3 v v ccio 2.5 v v ccio 1.5 v v ccio 1.8 v v ccio level shifter shift tdo to level accepted by tester if necessary must be 1.8 v tolerant must be 2.5 v tolerant must be 3.3 v tolerant tdi tdo
altera corporation 14?17 february 2007 cyclone ii device handbook, volume 1 ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices when designing a board for jtag conf iguration of cyclone ii devices, the connections for the dedicated configur ation pins need to be considered. f for more information on using the ie ee std.1149.1 circuitry for device configuration, see the configuring cyclone ii devices chapter in volume 1 of the cyclone ii device handbook . bst for configured devices for a configured device, the input buffers are turned off by default for i/o pins that are set as output only in the design file. nevertheless, executing the sample instruction will turn on the input buffers for the output pins. you can set the quartus ii software to always enable the input buffers on a configured device so it behaves the same as an unconfigured device for boundary-scan testing, allowing sample function on output pins in the de sign. this aspect can cause slight increase in standby current because th e unused input buff er is always on. in the quartus ii software, do the following: 1. choose settings (assignment menu). 2. click assembler . 3. turn on always enable input buffers . 4. if you use the default setting with input disabled, you need to convert the default bsdl file to th e design-specific bsdl file using the bsdlcustomizer script. for more information regarding bsdl file, refer to ?boundary-scan descript ion language (bsdl) support? .
14?18 altera corporation cyclone ii device handbook, volume 1 february 2007 disabling ieee std. 1149.1 bst circuitry disabling ieee std. 1149.1 bst circuitry the ieee std. 1149.1 bst circuitry fo r cyclone ii devices is enabled upon device power-up. because this circuitr y may be used for bst or in-circuit reconfiguration, this circuitry must be enabled only at specific times as mentioned in ?using ieee std. 1149.1 bst circuitry? on page 14?16 . if the ieee std. 1149.1 circuitry will not be utilized at any time, the circuitry should be permanently disabled. table 14?3 shows the pin connections necessary for disabling the ieee std. 1149.1 circuitry in cyclone ii devices to ensure that the ci rcuitry is not inadvertently enabled when it is not needed. guidelines for ieee std. 1149.1 boundary-scan testing use the following guidelines when performing boundary-scan testing with ieee std. 1149.1 devices: if the 10-bit checkerboard patt ern ?1010101010? does not shift out of the instruction register via the tdo pin during the fi rst clock cycle of the shift_ir state, the tap controller has not reached the proper state. to solve this problem, try one of the following procedures: verify that the tap controller has reached the shift_ir state correctly. to advance the tap controller to the shift_ir state, return to the reset state and send the code 01100 to the tms pin. check the connections to the v cc , gnd, jtag, and dedicated configuration pins on the device. table 14?3. disabling ieee std. 1149.1 circuitry jtag pins (1) connection for disabling tms v cc tck gnd tdi v cc tdo leave open note to table 14?3 : (1) there is no software option to disable jtag in cyclone ii devices. the jtag pins are dedicated.
altera corporation 14?19 february 2007 cyclone ii device handbook, volume 1 ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices perform a sample/preload test cycle prior to the first extest test cycle to ensure that known data is present at the device pins when the extest mode is entered. if the oej update register contains a 0, the data in the outj update register is driven out. the state must be known and correct to avoid contention with other devices in the system. do not perform extest testing during icr. this instruction is supported before or after icr, but not during icr. use the config_io instruction to interrupt configuration, then perform testing, or wait for configuration to complete. if performing testing before configuration, hold the nconfig pin low. after configuration, an y pins in a differential pin pair cannot be tested. therefore, performing bst after configuration requires editing bsc group definitions that correspond to these differential pin pairs. the bsc group should be redefined as an internal cell. see the bsdl file for more information on editing. for more information on boundary scan testing, contact altera applications. boundary-scan description language (bsdl) support the boundary-scan description lang uage (bsdl), a subset of vhdl, provides a syntax that allows yo u to describe the features of an ieee std. 1149.1 bst-capable device that can be tested. test software development systems then use the bsdl files for test generation, analysis, and failure diagnostics. fo r more information, or to receive bsdl files for ieee std. 1149.1-compliant cyclone ii devices, visit the altera web site at www.altera.com . conclusion the ieee std. 1149.1 bst circuitr y available in cyclone ii devices provides a cost-effective and effici ent way to test systems that contain devices with tight lead spacing. ci rcuit boards with altera and other ieee std. 1149.1-compliant devices can use the extest , sample/preload , bypass, idcode, usercode, clamp, and highz modes to create serial patterns that internally test th e pin connections between devices and check device operation. references bleeker, h., p. van den eijnden, and f. de jong. boundary-scan test: a practical approach . eindhoven, the netherla nds: kluwer academic publishers, 1993. institute of electrical and electronics engineers, inc. ieee standard test access port and boundary-scan architecture (ieee std 1149.1-2001). new york: institute of electrical and electronics engineers, inc., 2001.
14?20 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history maunder, c. m., and r. e. tulloss. the test access port and boundary-scan architecture . los alamitos: ieee comp uter society press, 1990. document revision history table 14?4 shows the revision history for this document. table 14?4. document revision history date & document version changes made summary of changes february 2007 v2.1 added document revision history. added new section ?bst for configured devices? . added infomation about ?always enable input buffer? option. july 2005 v2.0 moved the ?jtag timing specifications? section to the dc characteristics & timing specifications chapter. june 2004 v1.0 added document to the cyclone ii device handbook.
altera corporation section vii?1 preliminary section vii. pcb layout guidelines this section provides informatio n for board layout designers to successfully layout their boards for cyclone ? ii devices. the chapters in this section contain the required pcb layout guidelines and package specifications. this section includes the following chapters: chapter 15, package information for cyclone ii devices revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in the complete handbook.
section vii?2 altera corporation preliminary revision history cyclone ii device handbook, volume 1
altera corporation 15?1 february 2007 15. package information for cyclone ii devices introduction this chapter provides pack age information for altera ? cyclone ? ii devices, including: device and package cross reference thermal resistance values package outlines table 15?1 shows cyclone ii device package options. table 15?1. cyclone ii device package options device package pins ep2c5 plastic thin quad flat pack (tqfp) ? wirebond 144 plastic quad flat pack (pqfp) ? wirebond 208 low profile fineline bga ? ? wirebond 256 ep2c8 tqfp ? wirebond 144 pqfp ? wirebond 208 low profile fineline bga ? wirebond 256 ep2c15 low profile fineline bga, option 2 ? wirebond 256 fineline bga, option 3? wirebond 484 ep2c20 pqfp ? wirebond 240 low profile fineline bga, option 2 ? wirebond 256 fineline bga, option 3? wirebond 484 ep2c35 fineline bga, option 3 ? wirebond 484 ultra fineline bga ? wirebond 484 fineline bga, option 3 ? wirebond 672 ep2c50 fineline bga, option 3 ? wirebond 484 ultra fineline bga ? wirebond 484 fineline bga, option 3 ? wirebond 672 ep2c70 fineline bga, option 3 ? wirebond 672 fineline bga ? wirebond 896 cii51015-2.3
15?2 altera corporation cyclone ii device handbook, volume 1 february 2007 thermal resistance thermal resistance thermal resistance values for cyclon e ii devices are provided for a board meeting jedec specifications and for a typical board. the values provided are as follows: ja ( c/w) still air?junction-to-ambi ent thermal resistance with no airflow when a heat sink is not being used. ja ( c/w) 100 ft./minute?junction- to-ambient thermal resistance with 100 ft./minute airflow when a heat sink is not being used. ja ( c/w) 200 ft./minute?junction- to-ambient thermal resistance with 200 ft./minute airflow when a heat sink is not being used. ja ( c/w) 400 ft./minute?junction- to-ambient thermal resistance with 400 ft./minute airflow when a heat sink is not being used. jc ( c/w)?junction-to-case thermal resistance for device. jb ( c/w)?junction-to-board thermal resistance for specific board being used. table 15?2 provides ja (junction-to-ambient thermal resistance) values and jc (junction-to-case thermal resistance) values for cyclone ii devices on a board meeting jedec specifications for thermal resistance calculation. the jedec board specifications require two signal and two power/ground planes and are available at www.jedec.org . table 15?2. thermal resistance of cyclone ii devices fo r board meeting jedec s pecifications (part 1 of 2) device pin count package ja ( c/w) still air ja ( c/w) 100 ft./min. ja ( c/w) 200 ft./min. ja ( c/w) 400 ft./min. jc ( c/w) ep2c5 144 tqfp 31 29.3 27.9 25.5 10 208 pqfp 30.4 29.2 27.3 22.3 5.5 256 fineline bga 30.2 26.1 23.6 21.7 8.7 ep2c8 144 tqfp 29.8 28.3 26.9 24.9 9.9 208 pqfp 30.2 28.8 26.9 21.7 5.4 256 fineline bga 27 23 20.5 18.5 7.1 ep2c15 256 fineline bga 24.2 20 17.8 16 5.5 484 fineline bga 21 17 14.8 13.1 4.2 ep2c20 240 pqfp 26.6 24 21.4 17.4 4.2 256 fineline bga 24.2 20 17.8 16 5.5 484 fineline bga 21 17 14.8 13.1 4.2 ep2c35 484 fineline bga 19.4 15.4 13.3 11.7 3.3 484 ultra fineline bga 20.6 16.6 14.5 12.8 5 672 fineline bga 18.6 14.6 12.6 11.1 3.1
altera corporation 15?3 february 2007 cyclone ii device handbook, volume 1 package information for cyclone ii devices table 15?3 provides board dimension information for each package. ep2c50 484 fineline bga 18.4 14.4 12.4 10.9 2.8 484 ultra fineline bga 19.6 15.6 13.6 11.9 4.4 672 fineline bga 17.7 13.7 11.8 10.2 2.6 ep2c70 672 fineline bga 16.9 13 11.1 9.7 2.2 896 fineline bga 16.3 11.9 10.5 9.1 2.1 table 15?2. thermal resistance of cyclone ii devices fo r board meeting jedec s pecifications (part 2 of 2) device pin count package ja ( c/w) still air ja ( c/w) 100 ft./min. ja ( c/w) 200 ft./min. ja ( c/w) 400 ft./min. jc ( c/w) table 15?3. pcb dimensions notes (1) , (2) 2.5 mm thick signal layers power/ground layers package dimension (mm) board dimension (mm) f896 10 10 31 91 f672 8 8 27 87 f672 7 7 27 87 f484 7 7 23 83 f484 6 6 23 83 u484 7 7 19 79 u484 6 6 19 79 f256 6 6 17 77 notes to ta b l e 1 5 ? 3 : (1) power layer cu thickness 35 um, cu 90% (2) signal layer cu thickness 17 um, cu 15%
15?4 altera corporation cyclone ii device handbook, volume 1 february 2007 package outlines table 15?4 provides ja (junction-to-ambient thermal resistance) values, jc (junction-to-case thermal resistance) values, jb (junction-to-board thermal resistance) values for cyclone ii devices on a typical board. package outlines the package outlines on the follow ing pages are listed in order of ascending pin count. 144-pin plastic thin quad flat pack (tqfp) ? wirebond all dimensions and tolerances conform to asme y14.5m ? 1994. controlling dimension is in millimeters. pin 1 may be indicated by an id dot, or a special feature, in its proximity on package surface. table 15?4. thermal resistance of cyclone ii devices for typical board device pin count package ja ( c/w) still air ja ( c/w) 100 ft./min. ja ( c/w) 200 ft./min. ja ( c/w) 400 ft./min. jc ( c/w) jb ( c/w) ep2c5 256 fineline bga 30.2 25.8 22.9 20.6 8.7 14.8 ep2c8 256 fineline bga 27.9 23.2 20.5 18.4 7.1 12.3 ep2c15 256 fineline bga 24.7 20.1 17.5 15.3 5.5 9.1 484 fineline bga 20.5 16.2 13.9 12.2 4.2 7.2 ep2c20 256 fineline bga 24.7 20.1 17.5 15.3 5.5 9.1 484 fineline bga 20.5 16.2 13.9 12.2 4.2 7.2 ep2c35 484 fineline bga 18.8 14.5 12.3 10.6 3.3 5.7 484 ultra fineline bga 20 15.5 13.2 11.3 5 5.3 672 fineline bga 17.4 13.3 11.3 9.8 3.1 5.5 ep2c50 484 fineline bga 17.7 13.5 11.4 9.8 2.8 4.5 484 fineline bga 18.1 13.8 11.7 10.1 2.8 4.6 484 ultra fineline bga 19 14.6 12.3 10.6 4.4 4.4 484 ultra fineline bga 19.4 15 12.7 10.9 4.4 4.6 672 fineline bga 16.5 12.4 10.5 9 2.6 4.6 ep2c70 672 fineline bga 15.7 11.7 9.8 8.3 2.2 3.8 672 fineline bga 15.9 11.9 9.9 8.4 2.2 3.9 896 fineline bga 14.6 10.7 8.9 7.6 2.1 3.7
altera corporation 15?5 february 2007 cyclone ii device handbook, volume 1 package information for cyclone ii devices tables 15?5 and 15?6 show the package information and package outline figure references, respectively , for the 144-pin tqfp package. table 15?5. 144-pin tqfp package information description specification ordering code reference t package acronym tqfp lead frame material copper lead finish (plating) regular: 85sn:15pb (typ.) pb-free: matte sn jedec outline reference ms-026 variation: bfb maximum lead coplanarity 0.003 inches (0.08mm) weight 1.3 g moisture sensitivity level printed on moisture barrier bag table 15?6. 144-pin tqfp package outline dimensions symbol millimeter min. nom. max. a??1.60 a1 0.05 ? 0.15 a2 1.35 1.40 1.45 d 22.00 bsc d1 20.00 bsc e 22.00 bsc e1 20.00 bsc l 0.45 0.60 0.75 l1 1.00 ref s0.20? ? b 0.17 0.22 0.27 c0.09?0.20 e 0.50 bsc 0 3.5 7
15?6 altera corporation cyclone ii device handbook, volume 1 february 2007 package outlines figure 15?1 shows a 144-pin tqfp package outline. figure 15?1. 144-pin tqfp package outline pin 1 id e e1 d1 d pin 144 s l l1 detail a gage plane 0.25mm c b e see detail a pin 1 a a2 a1 pin 36
altera corporation 15?7 february 2007 cyclone ii device handbook, volume 1 package information for cyclone ii devices 208-pin plastic quad flat pack (pqfp) ? wirebond all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin 1 may be indicated by an id dot in its proximity on package surface. tables 15?7 and 15?8 show the package information and package outline figure references, respectively, for the 208-pin pqfp package. table 15?7. 208-pin pqfp package information description specification ordering code reference q package acronym pqfp lead material copper lead finish (plating) regular: 85sn:15pb (typ.) pb-free: matte sn jedec outline reference ms-029 variation: fa-1 maximum lead coplanarity 0.003 inches (0.08 mm) weight 5.7 g moisture sensitivity level printed on moisture barrier bag table 15?8. 208-pin pqfp package ou tline dimensions (part 1 of 2) symbol millimeter min. nom. max. a??4.10 a1 0.25 ? 0.50 a2 3.20 3.40 3.60 d 30.60 bsc d1 28.00 bsc e 30.60 bsc e1 28.00 bsc l 0.50 0.60 0.75 l1 1.30 ref s0.20? ? b0.17?0.27 c0.09?0.20
15?8 altera corporation cyclone ii device handbook, volume 1 february 2007 package outlines figure 15?2 shows a 208-pin pqfp package outline. figure 15?2. 208-pin pqfp package outline e 0.50 bsc q03.58 table 15?8. 208-pin pqfp package ou tline dimensions (part 2 of 2) symbol millimeter min. nom. max. pin 1 id e d1 d pin 208 a a2 a1 s l l1 detail a gage plane 0.25mm c b e see detail a e1 pin 1 pin 52
altera corporation 15?9 february 2007 cyclone ii device handbook, volume 1 package information for cyclone ii devices 240-pin plastic quad flat pack (pqfp) all dimensions and tolerances conform to asme y14.5m ? 1994. controlling dimension is in millimeters. pin 1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 15?9 and 15?10 show the package inform ation and package outline figure references, respectively, for the 240-pin pqfp package. table 15?9. 240-pin pqfp package information description specification ordering code reference q package acronym pqfp leadframe material copper lead finish (plating) regular: 85sn:15pb (typ.) pb-free: matte sn jedec outline reference ms-029 variation: ga maximum lead coplanarity 0.003 inches (0.08mm) weight 7.0 g moisture sensitivity level printed on moisture barrier bag table 15?10. 240-pin pqfp package outline dimensions (part 1 of 2) symbol millimeter min. nom. max. a??4.10 a1 0.25 ? 0.50 a2 3.20 3.40 3.60 d 34.60 bsc d1 32.00 bsc e 34.60 bsc e1 32.00 bsc l 0.45 0.60 0.75 l1 1.30 ref s0.20? ? b0.17?0.27 c0.09?0.20
15?10 altera corporation cyclone ii device handbook, volume 1 february 2007 package outlines figure 15?3 shows a 240-pin pqfp package outline. figure 15?3. 240-pin pqfp package outline e 0.50 bsc 0 3.5 8 table 15?10. 240-pin pqfp package outline dimensions (part 2 of 2) symbol millimeter min. nom. max. s l l1 detail a gage plane 0.25mm c b e see detail a d d1 e e1 a2 a a1 pin 1 id pin 1 pin 60 pin 240
altera corporation 15?11 february 2007 cyclone ii device handbook, volume 1 package information for cyclone ii devices 256-pin fineline ball-grid array, option 2 ? wirebond all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on the package surface. 1 this pod is applicable to th e f256 package of the cyclone ii product only. tables 15?11 and 15?12 show the package information and package outline figure references, respectively, for the 256-pin fineline bga package. table 15?11. 256-pin fineline bga package information description specification ordering code reference f package acronym fineline bga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference mo- 192 variation: aaf-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 1.9 g moisture sensitivity level printed on moisture barrier bag table 15?12. 256-pin fineline bga package outline dimensions symbol millimeter min. nom. max. a??1.55 a1 0.25 ? ? a2 1.05 ref a3 ? ? 0.80 d 17.00 bsc e 17.00 bsc b 0.40 0.50 0.55 e1.00 bsc
15?12 altera corporation cyclone ii device handbook, volume 1 february 2007 package outlines figure 15?4 shows a 256-pin finelin e bga package outline. figure 15?4. 256-pin fineline bga package outline d e pin a1 id b e e a3 a1 a2 a pin a1 corner bottom view top view
altera corporation 15?13 february 2007 cyclone ii device handbook, volume 1 package information for cyclone ii devices 484-pin fineline bga, option 3 ? wirebond all dimensions and tolerances conform to asme y14.5m ? 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 15?13 and 15?14 show the package information and package outline figure references, respectively, for the 484-pin fineline bga package. table 15?13. 484-pin fineline bga package information description specification ordering code reference f package acronym fineline bga substrate material bt solder ball composition r egular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aaj-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 5.7 g moisture sensitivity level printed on moisture barrier bag table 15?14. 484-pin fineline bga package outline dimensions symbol millimeter min. nom. max. a??2.60 a1 0.30 ? ? a2 ? ? 2.20 a3 ? ? 1.80 d 23.00 bsc e 23.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
15?14 altera corporation cyclone ii device handbook, volume 1 february 2007 package outlines figure 15?5 shows a 484-pin finelin e bga package outline. figure 15?5. 484-pin fineline bga package outline d e pin a1 id b e a1 a2 pin a1 corner a v u r t p l n m k j 2 f h g e d a b c 1 a3 top view bottom view aa ab y w 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 e
altera corporation 15?15 february 2007 cyclone ii device handbook, volume 1 package information for cyclone ii devices 484-pin ultra fineline bga ? wirebond all dimensions and tolerances conform to asme y14.5m ? 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 15?15 and 15?16 show the package information and package outline figure references, respecti vely, for the 484-pin ultra fineline bga package. table 15?15. 484-pin ultra fineline bga package information description specification ordering code reference u package acronym ubga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference m o-216 variation: bap-2 maximum lead coplanarity 0.005 inches (0.12mm) weight 1.8 g moisture sensitivity level printed on moisture barrier bag table 15?16. 484-pin ultra fineline bga package out line dimensions symbol millimeter min. nom. max. a??2.20 a1 0.20 ? ? a2 0.65 ? ? a3 0.80 typ d 19.00 bsc e 19.00 bsc b 0.40 0.50 0.60 e 0.80 bsc
15?16 altera corporation cyclone ii device handbook, volume 1 february 2007 package outlines figure 15?6 shows a 484-pin ultra fineline bga package outline. figure 15?6. 484-pin ultra finel ine bga package outline bottom view top view d e pin a1 id b a3 a1 a2 a pin a1 corner e e
altera corporation 15?17 february 2007 cyclone ii device handbook, volume 1 package information for cyclone ii devices 672-pin fineline bga package, option 3 ? wirebond all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on the package surface. tables 15?17 and 15?18 show the package in formation and package outline figure references, respecti vely, for the 672-pin fineline bga package. table 15?17. 672-pin fineline bga package information description specification ordering code reference f package acronym fineline bga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aal-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 7.7 g moisture sensitivity level printed on moisture barrier bag table 15?18. 672-pin fineline bga package outline dimensions symbol dimensions (mm) min. nom. max. a??2.60 a1 0.30 ? ? a2 ? ? 2.20 a3 ? ? 1.80 d 27.00 bsc e 27.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
15?18 altera corporation cyclone ii device handbook, volume 1 february 2007 package outlines figure 15?7 shows a 672-pin finelin e bga package outline. figure 15?7. 672-pin fineline bga package outline 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 e d e pin a1 id b e a1 a2 pin a1 corner a v u r t p l n m k j 2 f h g e d a b c 1 aa ab y w 3 4 5 25 23 26 24 ae af ac ad a3 bottom view top view
altera corporation 15?19 february 2007 cyclone ii device handbook, volume 1 package information for cyclone ii devices 896-pin fineline bga package ? wirebond all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1?s location may be indicated by an id dot in its proximity on the package surface. tables 15?19 and 15?20 show the package in formation and package outline figure references, respecti vely, for the 896-pin fineline bga. table 15?19. 896-pin fineline bga package information description specification ordering code reference f package acronym fineline bga substrate material bt solder ball composition regular: 63sn: 37pb (typical) pb-free: sn: 3.0ag: 0.5cu (typical) jedec outline reference ms-034 variation aan-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 11.5 g moisture sensitivity level printed on moisture barrier bag table 15?20. 896-pin fineline bga package outline dimensions symbol dimensions (mm) min. nom. max. a??2.60 a1 0.30 ? ? a2 ? ? 2.20 a3 ? ? 1.80 d 31.00 bsc e 31.00 bsc b 0.50 0.60 0.70 e 1.00 bsc
15?20 altera corporation cyclone ii device handbook, volume 1 february 2007 package outlines figure 15?8 shows a 896-pin finelin e bga package outline. figure 15?8. 896-pin fineline bga package outline 25 23 26 24 ae af ac ad 27 29 30 28 ag ak aj ah a3 bottom view top view 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 e d e pin a1 id b e a1 a2 pin a1 corner a v u r t p l n m k j 2 f h g e d a b c 1 aa ab y w 3 4 5
altera corporation 15?21 february 2007 cyclone ii device handbook, volume 1 package information for cyclone ii devices document revision history table 15?21 shows the revision history for this document. table 15?21. document revision history date & document version changes made summary of changes february 2007 v2.3 added document revision history. november 2005 v2.1 updated information throughout. july 2005 v2.0 updated packaging information. november 2004 v1.0 added document to the cyclone ii device handbook.
15?22 altera corporation cyclone ii device handbook, volume 1 february 2007 document revision history

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